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* Fix ARM tests to be register allocator independent.Jakob Stoklund Olesen2011-03-311-10/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128680 91177308-0d34-0410-b5e6-96231b3b80d8
* Making use of VFP / NEON floating point multiply-accumulate / subtraction isEvan Cheng2010-12-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-031-1/+0
| | | | | | | | | | | | | | 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
* putback r116983 and fix simple-fp-encoding.ll testsAndrew Trick2010-10-211-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r116983, which is breaking all the buildbots.Owen Anderson2010-10-211-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing scheduling itineraries for transfers between core registers and ↵Evan Cheng2010-10-211-1/+2
| | | | | | VFP registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct some load / store instruction itinerary mistakes:Evan Cheng2010-10-091-1/+1
| | | | | | | | | 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
* Change register allocation order for ARM VFP and NEON registers to put theBob Wilson2010-10-081-17/+17
| | | | | | | | | | | | | | | | | callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert VLD1 and VLD2 instructions to use pseudo-instructions untilBob Wilson2010-09-021-1/+1
| | | | | | | after regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
* Add alignment arguments to all the NEON load/store intrinsics.Bob Wilson2010-08-271-32/+33
| | | | | | | | Update all the tests using those intrinsics and add support for auto-upgrading bitcode files with the old versions of the intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112271 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace some NEON vmovl intrinsic that I missed earlier.Bob Wilson2010-08-201-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111696 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to representBob Wilson2010-07-131-1/+1
| | | | | | | NEON VMOV-immediate instructions. This simplifies some things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
* Print "dregpair" NEON operands with a space between them, for readability andBob Wilson2010-07-091-2/+2
| | | | | | | consistency with other instructions that have lists of register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
* Reenable DAG combining for vector shuffles. It looks like it was temporarilyBob Wilson2010-07-091-1/+0
| | | | | | | | | disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the other half of the BRCOND optimization, and updateDan Gohman2010-06-241-2/+2
| | | | | | | as many tests as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106749 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove arm_apcscc from the test files. It is the default and doing thisRafael Espindola2010-06-171-4/+4
| | | | | | matches what llvm-gcc and clang now produce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some latency computation bugs: if the use is not a machine opcode do not ↵Evan Cheng2010-05-281-3/+4
| | | | | | just return zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ARM scheduling default to list-hybrid if the target supports floating ↵Evan Cheng2010-05-211-6/+6
| | | | | | point instructions (and is not using soft float). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
* TwoAddressInstructionPass doesn't really know how to merge live intervals whenJakob Stoklund Olesen2010-05-191-0/+17
| | | | | | | | lowering REG_SEQUENCE instructions. Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104146 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7162: Use source register classes and sub-indices to determine the ↵Evan Cheng2010-05-181-0/+38
| | | | | | correct register class of the definitions of REG_SEQUENCE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other ↵Evan Cheng2010-05-171-0/+35
| | | | | | REG_SEQUENCE instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103994 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace ↵Evan Cheng2010-05-171-0/+46
| | | | | | it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103984 91177308-0d34-0410-b5e6-96231b3b80d8
* Careful with reg_sequence coalescing to not to overwrite sub-register indices.Evan Cheng2010-05-171-0/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103971 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn on -neon-reg-sequence by default.Evan Cheng2010-05-171-0/+170
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
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