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* Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging....Stephen Lin2013-07-131-8/+8
* Extend r148086 to check for [r +/- reg] address mode. This fixes queens perfo...Evan Cheng2012-03-061-4/+8
* DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng2012-01-131-4/+4
* Remove a check from ARM shifted operand isel helper methods, which were blockingCameron Zwarich2011-10-051-5/+4
* Be careful about scheduling nodes above previous calls. It increase usages ofEvan Cheng2011-04-261-1/+1
* Minor optimization. sign-ext/anyext of undef is still undef.Evan Cheng2011-03-141-5/+5
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-281-1/+1
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ...Evan Cheng2010-10-281-1/+1
* - Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng2010-10-281-1/+1
* Shifter ops are not always free. Do not fold them (especially to formEvan Cheng2010-10-271-9/+63
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-091-2/+2
* Remove llvm-upgrade.Tanya Lattner2008-02-171-11/+14
* For PR1319: Upgrade to use new test harnessReid Spencer2007-04-151-1/+1
* Fix test case.Evan Cheng2007-02-281-2/+2
* ARM test cases contributed by Apple.Evan Cheng2007-01-191-0/+15