aboutsummaryrefslogtreecommitdiffstats
path: root/test/CodeGen/ARM
Commit message (Collapse)AuthorAgeFilesLines
* Don't fast-isel for atomic load/store; some cases require extra handling ↵Eli Friedman2011-09-021-0/+1
| | | | | | missing from fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139044 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r131152, r129796, r129761. This code is currently consideredDan Gohman2011-09-011-0/+4
| | | | | | | | | to be unreliable on platforms which require memcpy calls, and it is complicating broader legalize cleanups. It is hoped that these cleanups will make memcpy byval easier to implement in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138977 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't drop alignment info on local common symbols.Benjamin Kramer2011-09-012-5/+20
| | | | | | | | | | | - On COFF the .lcomm directive has an alignment argument. - On ELF we fall back to .local + .comm Based on a patch by NAKAMURA Takumi. Fixes PR9337, PR9483 and PR10128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138976 91177308-0d34-0410-b5e6-96231b3b80d8
* Permit remat of partial register defs when it is safe.Jakob Stoklund Olesen2011-09-011-0/+24
| | | | | | | | | | | | | | | | | An instruction may define part of a register where the other bits are undefined. In that case, it is safe to rematerialize the instruction. For example: %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def> The extra <imp-def> operand indicates that the instruction does not read the other parts of the virtual register, so a remat is safe. This patch simply allows multiple def operands for the virtual register. It is MI->readsVirtualRegister() that determines if we depend on a previous value so remat is impossible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138953 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent remat of partial register redefinitions.Jakob Stoklund Olesen2011-09-011-0/+28
| | | | | | | | | | | | | An instruction that redefines only part of a larger register can never be rematerialized since the virtual register value depends on the old value in other parts of the register. This was fixed for the inline spiller in r138794. This patch fixes the problem for all register allocators, and includes a small test case. <rdar://problem/10032939> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138944 91177308-0d34-0410-b5e6-96231b3b80d8
* Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; ↵Eli Friedman2011-08-311-7/+37
| | | | | | implements 64-bit atomic load/store for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138872 91177308-0d34-0410-b5e6-96231b3b80d8
* 64-bit atomic cmpxchg for ARM.Eli Friedman2011-08-311-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138868 91177308-0d34-0410-b5e6-96231b3b80d8
* Some minor cleanups for r138845.Eli Friedman2011-08-311-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138846 91177308-0d34-0410-b5e6-96231b3b80d8
* Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman2011-08-311-0/+83
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138845 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng2011-08-301-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
* Add testcase for r138746.Owen Anderson2011-08-291-0/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138747 91177308-0d34-0410-b5e6-96231b3b80d8
* Atomic load/store on ARM/Thumb.Eli Friedman2011-08-261-0/+31
| | | | | | | | | | | | | | I don't really like the patterns, but I'm having trouble coming up with a better way to handle them. I plan on making other targets use the same legalization ARM-without-memory-barriers is using... it's not especially efficient, but if anyone cares, it's not that hard to fix for a given target if there's some better lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM fix for missing implicit operands on ldmia_ret.Andrew Trick2011-08-251-0/+100
| | | | | | | rdar://10005094: miscompile of 176.gcc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138568 91177308-0d34-0410-b5e6-96231b3b80d8
* With the fix in r138164: "Add <imp-def> operands to QQ and QQQQ stack loads."Chad Rosier2011-08-201-1/+1
| | | | | | -verify-machineinstrs can be enabled for this test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138171 91177308-0d34-0410-b5e6-96231b3b80d8
* VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg.Chad Rosier2011-08-201-3/+2
| | | | | | | Therefore, rather then generate a pseudo instruction, which is later expanded, generate the necessary instructions in place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not use named md nodes to track variables that are completely optimized. ↵Devang Patel2011-08-191-2/+2
| | | | | | This does not scale while doing LTO with debug info. New approach is to include list of variables in the subprogram info directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138145 91177308-0d34-0410-b5e6-96231b3b80d8
* Use regex to remove false dependencies on register allocation.Jim Grosbach2011-08-191-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138137 91177308-0d34-0410-b5e6-96231b3b80d8
* Update tests.Jim Grosbach2011-08-191-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138116 91177308-0d34-0410-b5e6-96231b3b80d8
* FastISel: avoid function calls between the materialization of the constant ↵Ivan Krasin2011-08-181-1/+1
| | | | | | and its use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137993 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb assembly parsing and encoding for ADR.Jim Grosbach2011-08-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137864 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix this test to avoid leaving a temporary file behind.Eric Christopher2011-08-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137651 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand VMOVQQQQ pseudo instructions.Bob Wilson2011-08-131-0/+13
| | | | | | | Apparently we never added code to expand these pseudo instructions, and in over a year, no one has noticed. Our register allocator must be awesome! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137551 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM push of a single register encodes as pre-indexed STR.Jim Grosbach2011-08-111-1/+1
| | | | | | | | Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach2011-08-111-1/+1
| | | | | | | | Per the ARM ARM, a 'pop' of a single register encodes as an LDR, not an LDM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
* While extending definition range of a debug variable, consult lexical scopes ↵Devang Patel2011-08-101-1/+1
| | | | | | also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137250 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the R and Q constraints.Rafael Espindola2011-08-101-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137217 91177308-0d34-0410-b5e6-96231b3b80d8
* Inflate register classes after coalescing.Jakob Stoklund Olesen2011-08-092-3/+7
| | | | | | | | | | | | | | | | | | | | | | | Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137133 91177308-0d34-0410-b5e6-96231b3b80d8
* print st_shndx with the correct number of bits.Rafael Espindola2011-08-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136880 91177308-0d34-0410-b5e6-96231b3b80d8
* print st_other with the correct number of bits.Rafael Espindola2011-08-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136877 91177308-0d34-0410-b5e6-96231b3b80d8
* print st_type with the correct number of bits.Rafael Espindola2011-08-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136875 91177308-0d34-0410-b5e6-96231b3b80d8
* Print st_bind with the correct number of bits.Rafael Espindola2011-08-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136874 91177308-0d34-0410-b5e6-96231b3b80d8
* Print r_sym with the correct number of bits.Rafael Espindola2011-08-041-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136873 91177308-0d34-0410-b5e6-96231b3b80d8
* Print r_type with the correct number of bits.Rafael Espindola2011-08-041-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136872 91177308-0d34-0410-b5e6-96231b3b80d8
* Change anther counter to decimal.Rafael Espindola2011-08-041-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136870 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't print a counter in hex.Rafael Espindola2011-08-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136869 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove underscore that's breaking linux buildbots.Benjamin Kramer2011-08-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136833 91177308-0d34-0410-b5e6-96231b3b80d8
* Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics.Jakub Staszak2011-08-032-5/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136826 91177308-0d34-0410-b5e6-96231b3b80d8
* Use byte offset, instead of element number, to access merged global.Devang Patel2011-08-031-0/+124
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136759 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the 'Q' constraint.Eric Christopher2011-07-291-0/+12
| | | | | | | Fixes rdar://9866494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
* Transfer implicit operands in NEONMoveFixPass.Jakob Stoklund Olesen2011-07-291-0/+21
| | | | | | | | | Later passes /are/ using this information when running the register scavenger. This fixes the second problem in PR10520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136440 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -verify-arm-pseudo-expand.Jakob Stoklund Olesen2011-07-291-1/+1
| | | | | | | | | | This hidden llc option runs the machine code verifier after expanding ARM pseudo-instructions, but before if-conversion. The machine code verifier is much better at pointing out liveness errors that can trip up the register scavenger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136439 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle REG_SEQUENCE with implicitly defined operands.Jakob Stoklund Olesen2011-07-281-0/+21
| | | | | | | | | | | | | Code like that would only be produced by bugpoint, but we should still handle it correctly. When a register is defined by a REG_SEQUENCE of undefs, the register itself is undef. Previously, we would create a register with uses but no defs. Fixes part of PR10520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136401 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck'ize test.Jim Grosbach2011-07-261-20/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136135 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a crash when building 177.mesa for armv6.Jakob Stoklund Olesen2011-07-181-0/+32
| | | | | | | | | | | | When splitting a live range immediately before an LDR_POST instruction that redefines the address register, make sure to use the correct value number in leaveIntvBefore. We need the value number entering the instruction. <rdar://problem/9793765> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135413 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson2011-07-152-6/+6
| | | | | | to simplify the path towards an auto-generated disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a testcase for r135123.Eric Christopher2011-07-141-0/+14
| | | | | | Part of rdar://9761830 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135133 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve codegen for select's:Evan Cheng2011-07-131-0/+36
| | | | | | | | | | | | | | | | | | | | | if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify printing of ARM shifted immediates.Jim Grosbach2011-07-117-15/+15
| | | | | | | | | | Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing test for r134882.Cameron Zwarich2011-07-111-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134889 91177308-0d34-0410-b5e6-96231b3b80d8
* Be more aggressive about following hints.Jakob Stoklund Olesen2011-07-081-5/+6
| | | | | | | | | | | | | | | | | | | | RAGreedy::tryAssign will now evict interference from the preferred register even when another register is free. To support this, add the EvictionCost struct that counts how many hints are broken by an eviction. We don't want to break one hint just to satisfy another. Rename canEvict to shouldEvict, and add the first bit of eviction policy that doesn't depend on spill weights: Always make room in the preferred register as long as the evictees can be split and aren't already assigned to their preferred register. Also make the CSR avoidance more accurate. When looking for a cheaper register it is OK to use a new volatile register. Only CSR aliases that have never been used before should be avoided. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-06-25 11:21:19 +0000