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* When emitting a cmp with 0 for a lowered select, mask out the highDan Gohman2012-02-241-0/+19
| | | | | | | | bits of the value carying the boolean condition, as their contents are undefined. This fixes rdar://10887484. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151310 91177308-0d34-0410-b5e6-96231b3b80d8
* Make tests less sensitive to scheduling changes.Jakob Stoklund Olesen2012-02-232-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151260 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix to make sure that a comdat group gets generated correctly for a static ↵Anton Korobeynikov2012-02-231-0/+16
| | | | | | | | | | | member of instantiated C++ templates. Patch by Kristof Beyls! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151250 91177308-0d34-0410-b5e6-96231b3b80d8
* Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bitsEvan Cheng2012-02-231-2/+2
| | | | | | | | | of x are zero. This optimizes rev + lsr 16 to rev16. rdar://10750814 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151230 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng2012-02-231-0/+46
| | | | | | | | | | | | | | | | | | | | | | value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
* Proper support for a bastardized darwin-eabi hybird ABI.Evan Cheng2012-02-211-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151083 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for returning non-legal types with no sign- or zero-Chad Rosier2012-02-171-0/+9
| | | | | | | | entend flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150774 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace all instances of dg.exp file with lit.local.cfg, since all tests are ↵Eli Bendersky2012-02-162-5/+13
| | | | | | | | | | | run with LIT now and now Dejagnu. dg.exp is no longer needed. Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
* Tighten physical register invariants: Allocatable physical registers canLang Hames2012-02-141-1/+1
| | | | | | | only be live in to a block if it is the function entry point or a landing pad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150494 91177308-0d34-0410-b5e6-96231b3b80d8
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-102-2/+2
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for SUBs with non-legal types.Chad Rosier2012-02-081-0/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comment to test case.Chad Rosier2012-02-081-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150046 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for ORs with non-legal types.Chad Rosier2012-02-081-0/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150045 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for indirect branches.Chad Rosier2012-02-071-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150014 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for ADDs with non-legal types.Chad Rosier2012-02-061-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149934 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] HandlePHINodesInSuccessorBlocks() can promite i8 and i16 types too.Chad Rosier2012-02-041-0/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149730 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier2012-02-031-0/+52
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149706 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for selecting UIToFP.Chad Rosier2012-02-031-0/+94
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
* Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for ↵NAKAMURA Takumi2012-02-021-0/+26
| | | | | | | | now. It requires TARGETS=arm. I cannot reproduce a fixed issue with other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149604 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite instruction operands in AdjustCopiesBackFrom. Fixes PR11861.Lang Hames2012-01-271-0/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149097 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the use of isPredicable() with isPredicated() inChad Rosier2012-01-261-0/+44
| | | | | | | | | MachineBasicBlock::canFallThrough(). We're interested in the state of the instruction (i.e., is this a barrier or not?), not if the instruction is predicable or not. rdar://10501092 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149070 91177308-0d34-0410-b5e6-96231b3b80d8
* Clear kill flags before propagating a copy.Jakob Stoklund Olesen2012-01-261-0/+121
| | | | | | | | | | The live range of the source register may be extended when a redundant copy is eliminated. Make sure any kill flags between the two copies are cleared. This fixes PR11765. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149069 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve sub-register def handling in ProcessImplicitDefs.Jakob Stoklund Olesen2012-01-251-0/+24
| | | | | | | | | This boils down to using MachineOperand::readsReg() more. This fixes PR11829 where a use ended up after the first def when lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148996 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly emit ctors / dtors with priorities into desired sectionsAnton Korobeynikov2012-01-251-4/+6
| | | | | | | | | | and let linker handle the rest. This finally fixes PR5329 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148990 91177308-0d34-0410-b5e6-96231b3b80d8
* Set correct <def,undef> flags when lowering REG_SEQUENCE.Jakob Stoklund Olesen2012-01-242-1/+44
| | | | | | | | | | | | | | | | | | | | A REG_SEQUENCE instruction is lowered into a sequence of partial defs: %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0 %vreg7:ssub_1<def> = COPY %vreg2 %vreg7:ssub_2<def> = COPY %vreg2 %vreg7:ssub_3<def> = COPY %vreg2 The first def needs an <undef> flag to indicate it is the beginning of the live range, while the other defs are read-modify-write. Previously, we depended on LiveIntervalAnalysis to notice and fix the missing <def,undef>, but that solution was never robust, it was causing problems with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE instructions. This fixes PR11841. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148879 91177308-0d34-0410-b5e6-96231b3b80d8
* An option to selectively enable part of ARM EHABI support.Evgeniy Stepanov2012-01-241-0/+1
| | | | | | | | | This change adds an new option --arm-enable-ehabi-descriptors that enables emitting unwinding descriptors. This provides a mode with a working backtrace() without the (currently broken) exception support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148800 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth2012-01-241-3/+2
| | | | | | | | | | | | | | | | | | violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148759 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen2012-01-231-0/+105
| | | | | | This fixes a typo in r148589. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148724 91177308-0d34-0410-b5e6-96231b3b80d8
* An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov2012-01-231-2/+3
| | | | | | | | | This change adds an new value to the --arm-enable-ehabi option that disables emitting unwinding descriptors. This mode gives a working backtrace() without the (currently broken) exception support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148686 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-221-0/+68
| | | | | | | Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>Bob Wilson2012-01-201-0/+17
| | | | | | | | We have patterns for vector sext and zext operations but were missing anyext. Without those patterns, codegen will fail when the selection DAG has any_extend nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148568 91177308-0d34-0410-b5e6-96231b3b80d8
* VST2 four-register w/ update pseudos for fixed/register update.Jim Grosbach2012-01-201-0/+9
| | | | | | rdar://10724489 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148560 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov2012-01-191-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148473 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/ARM/test-sharedidx.ll: Fix for -Asserts.NAKAMURA Takumi2012-01-131-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148107 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng2012-01-132-4/+99
| | | | | | | | | | | | | | | | | overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Ld/St Optimizer fix.Andrew Trick2012-01-111-0/+46
| | | | | | | | | Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits. Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147922 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM updating VST2 pseudo-lowering fixed vs. register update.Jim Grosbach2012-01-101-0/+9
| | | | | | rdar://10663487 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147876 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow machine-cse to look across MBB boundary when cse'ing instructions thatEvan Cheng2012-01-101-1/+30
| | | | | | | | | | | define physical registers. It's currently very restrictive, only catching cases where the CE is in an immediate (and only) predecessor. But it catches a surprising large number of cases. rdar://10660865 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147827 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't print an unused label before .cfi_endproc.Rafael Espindola2012-01-091-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147763 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't print a label before .cfi_startproc when we don't need to. This makesRafael Espindola2012-01-071-3/+3
| | | | | | the produce assembly when using CFI just a bit more readable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147743 91177308-0d34-0410-b5e6-96231b3b80d8
* Use getRegForValue() to materialize the address of ARM globals.Jakob Stoklund Olesen2012-01-072-28/+16
| | | | | | | | | This enables basic local CSE, giving us 20% smaller code for consumer-typeset in -O0 builds. <rdar://problem/10658692> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147720 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a late machine instruction copy propagation pass. This catchesEvan Cheng2012-01-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | opportunities that only present themselves after late optimizations such as tail duplication .e.g. ## BB#1: movl %eax, %ecx movl %ecx, %eax ret The register allocator also leaves some of them around (due to false dep between copies from phi-elimination, etc.) This required some changes in codegen passes. Post-ra scheduler and the pseudo-instruction expansion passes have been moved after branch folding and tail merging. They were before branch folding before because it did not always update block livein's. That's fixed now. The pass change makes independently since we want to properly schedule instructions after branch folding / tail duplication. rdar://10428165 rdar://10640363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147716 91177308-0d34-0410-b5e6-96231b3b80d8
* Use movw+movt in ARMFastISel::ARMMaterializeGV.Jakob Stoklund Olesen2012-01-072-14/+28
| | | | | | | | | | | | | This eliminates a lot of constant pool entries for -O0 builds of code with many global variable accesses. This speeds up -O0 codegen of consumer-typeset by 2x because the constant island pass no longer has to look at thousands of constant pool entries. <rdar://problem/10629774> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147712 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable aligned NEON spilling by default.Jakob Stoklund Olesen2012-01-061-1/+1
| | | | | | Experiments show this to be a small speedup for modern ARM cores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147689 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-051-2/+1
| | | | | | | | | | | | Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147579 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix more places which should be checking for iOS, not darwin.Evan Cheng2012-01-0411-14/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-031-1/+2
| | | | | | | | | This patch caused a miscompilation of oggenc because a frame pointer was suddenly needed halfway through register allocation. <rdar://problem/10625436> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147487 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure DAGCombiner doesn't introduce multiple loads from the same memory ↵Eli Friedman2011-12-261-5/+5
| | | | | | location. PR10747, part 2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147283 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of copy-n-paste bugs. Noticed by George Russell!Chad Rosier2011-12-211-0/+58
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of copy-n-paste bugs. Noticed by George Russell.Evan Cheng2011-12-211-4/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
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