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* Start function numbering at 0.Dan Gohman2010-04-173-17/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101638 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR6847. RegScavenger should ignore DebugValues.Jakob Stoklund Olesen2010-04-151-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101392 91177308-0d34-0410-b5e6-96231b3b80d8
* add a simple dag combine to replace trivial shl+lshr withChris Lattner2010-04-151-1/+1
| | | | | | | and. This happens with the store->load narrowing stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101348 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operandBob Wilson2010-04-141-0/+16
| | | | | | | | does not have a legal type. The legalizer does not know how to handle those nodes. Radar 7854640. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle a v2f64 formal parameter that is split between registers and memoryBob Wilson2010-04-131-0/+7
| | | | | | | such that the entire second half is in memory. Radar 7855014. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101181 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a testcase for svn r100568.Bob Wilson2010-04-091-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100876 91177308-0d34-0410-b5e6-96231b3b80d8
* Split big test into multiple directories to cater toDale Johannesen2010-04-071-0/+33
| | | | | | | | those who don't build all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100688 91177308-0d34-0410-b5e6-96231b3b80d8
* switch the flag for using NEON for SP floating point to a subtarget 'feature'.Jim Grosbach2010-03-2511-22/+13
| | | | | | Re-commit. This time complete with testsuite updates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
* pr6652: Use LDM to restore PC to the return address on ARMv4.Bob Wilson2010-03-201-0/+13
| | | | | | | Patch by John Tytgat! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
* Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen2010-03-177-11/+11
| | | | | | | | | | | | | instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-167-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-167-11/+11
| | | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.Bob Wilson2010-03-165-5/+5
| | | | | | | | This does not move entirely to UAL syntax, since the default "increment after" suffix is empty but we still use "IA" for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98635 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typoAnton Korobeynikov2010-03-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98506 91177308-0d34-0410-b5e6-96231b3b80d8
* Feature test for half precision FP.Anton Korobeynikov2010-03-141-0/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98504 91177308-0d34-0410-b5e6-96231b3b80d8
* fix AsmPrinter::GetBlockAddressSymbol to always return a uniqueChris Lattner2010-03-141-3/+3
| | | | | | | | label instead of trying to form one based on the BB name (which causes collisions if the name is empty). This fixes PR6608 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98495 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable machine cse pass.Evan Cheng2010-03-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98132 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial bits of ARMv4-only support.Anton Korobeynikov2010-03-061-0/+13
| | | | | | Patch by John Tytgat! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97886 91177308-0d34-0410-b5e6-96231b3b80d8
* pr6478: The frame pointer spill frame index is only defined when there is aBob Wilson2010-03-041-0/+65
| | | | | | | frame pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97755 91177308-0d34-0410-b5e6-96231b3b80d8
* pr6480: Don't try producing ld/st-multiple instructions when the address isBob Wilson2010-03-041-0/+54
| | | | | | | | | an undef value. This is only going to come up for bugpoint-reduced tests -- correct programs will not access memory at undefined addresses -- so it's not worth the effort of doing anything more aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97745 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for comparisons of +/- zero when optimizing less-than-or-equal andBob Wilson2010-02-241-0/+16
| | | | | | | | | greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions. This is only allowed when UnsafeFPMath is set or when at least one of the operands is known to be nonzero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97065 91177308-0d34-0410-b5e6-96231b3b80d8
* Use NEON vmin/vmax instructions for floating-point selects.Bob Wilson2010-02-181-0/+65
| | | | | | | Radar 7461718. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96572 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr6111: Avoid using the LR register for the target address of an indirectBob Wilson2010-02-161-0/+14
| | | | | | | | | branch in ARM v4 code, since it gets clobbered by the return address before it is used. Instead of adding a new register class containing all the GPRs except LR, just use the existing tGPR class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96360 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply the new LoopStrengthReduction code, with compile time andDan Gohman2010-02-122-2/+28
| | | | | | | | | | | bug fixes, and with improved heuristics for analyzing foreign-loop addrecs. This change also flattens IVUsers, eliminating the stride-oriented groupings, which makes it easier to work with. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95975 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete dead PHI machine instructions. These can be created due to typeBob Wilson2010-02-101-3/+3
| | | | | | | | | | legalization even when the IR-level optimizer has removed dead phis, such as when the high half of an i64 value is unused on a 32-bit target. I had to adjust a few test cases that had dead phis. This is a partial fix for Radar 7627077. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95816 91177308-0d34-0410-b5e6-96231b3b80d8
* convert to filecheck.Chris Lattner2010-02-081-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95608 91177308-0d34-0410-b5e6-96231b3b80d8
* Run codegen dce pass for all targets at all optimization levels. Previously it'sEvan Cheng2010-02-064-187/+68
| | | | | | | | | | | only run for x86 with fastisel. I've found it being very effective in eliminating some obvious dead code as result of formal parameter lowering especially when tail call optimization eliminated the need for some of the loads from fixed frame objects. It also shrinks a number of the tests. A couple of tests no longer make sense and are now eliminated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95493 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.Anton Korobeynikov2010-01-301-4/+1
| | | | | | | | | Even if they are suported by the core, they can be disabled (this is just a configuration bit inside some register). Allow unaligned memops on darwin and conservatively disallow them otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94889 91177308-0d34-0410-b5e6-96231b3b80d8
* emit jump table an alias ".set" directives through MCStreamer as Chris Lattner2010-01-261-1/+1
| | | | | | | | | | | | | | assignments. .set x, a-b is the same as: x = a-b git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94596 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit .comm alignment in bytes but .align in powers of 2 for ARM ELF.Rafael Espindola2010-01-262-7/+7
| | | | | | | | Original patch by Sandeep Patel and updated by me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94582 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test for darwin.Rafael Espindola2010-01-251-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94421 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR6134.Rafael Espindola2010-01-252-9/+37
| | | | | | | | | We are not emitting alignments on Darwin for "bar". Not sure what is the correct way to do it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94400 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert LoopStrengthReduce.cpp to pre-r94061 for now.Dan Gohman2010-01-223-29/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94123 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-implement the main strength-reduction portion of LoopStrengthReduction.Dan Gohman2010-01-213-4/+29
| | | | | | | | | | | | | | | This new version is much more aggressive about doing "full" reduction in cases where it reduces register pressure, and also more aggressive about rewriting induction variables to count down (or up) to zero when doing so reduces register pressure. It currently uses fairly simplistic algorithms for finding reuse opportunities, but it introduces a new framework allows it to combine multiple strategies at once to form hybrid solutions, instead of doing all full-reduction or all base+index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94061 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r93758.Evan Cheng2010-01-191-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93824 91177308-0d34-0410-b5e6-96231b3b80d8
* The Neon "vtst" instruction takes a suffix that is the element size alone --Bob Wilson2010-01-171-6/+6
| | | | | | | | | adding an "i" to the suffix, indicating that the elements are integers, is accepted but not part of the standard syntax. This helps us pass a few more of the Neon tests from gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93677 91177308-0d34-0410-b5e6-96231b3b80d8
* Run the pre-register allocation tail duplication pass by default. RemoveBob Wilson2010-01-161-0/+4
| | | | | | | | the -pre-regalloc-taildup command-line option, and add a new -disable-early-taildup option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93597 91177308-0d34-0410-b5e6-96231b3b80d8
* remove uses of deprecated functions, this generates slightlyChris Lattner2010-01-131-3/+3
| | | | | | | | | | different BlockAddress labels, but nothing semantically important. Add a FIXME that BlockAddress codegen is broken if the LLVM BB has an empty name (e.g. strip was run). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93303 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete useless trailing semicolons.Dan Gohman2010-01-052-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this more likely to generate a libcall.Chris Lattner2010-01-011-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92387 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle ARM inline asm "w" constraints with 64-bit ("d") registers.Bob Wilson2009-12-181-0/+12
| | | | | | | | | The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
* - Support inline asm 'w' constraint for 128-bit vector types.Evan Cheng2009-12-081-0/+13
| | | | | | | - Also support the 'q' NEON registers asm code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90894 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize canonical forms of vector shuffles where the same vector is used forBob Wilson2009-12-031-0/+19
| | | | | | | | | both source operands. In the canonical form, the 2nd operand is changed to an undef and the shuffle mask is adjusted to only reference elements from the 1st operand. Radar 7434842. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90417 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR5614: parts of a physical register def may be killed the rest.Evan Cheng2009-12-011-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90180 91177308-0d34-0410-b5e6-96231b3b80d8
* Materialize global addresses via movt/movw pair, this is always betterAnton Korobeynikov2009-11-241-0/+20
| | | | | | | | | | | | | than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
* move fconst[sd] to UAL. <rdar://7414913>Jim Grosbach2009-11-232-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89700 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert ARM tests to FileCheck for PR5307.Edward O'Callaghan2009-11-227-35/+137
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89593 91177308-0d34-0410-b5e6-96231b3b80d8
* Forgot to alter RUN line when converting to FileCheck.Edward O'Callaghan2009-11-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89588 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for bad FileCheck converts in revision 89584.Edward O'Callaghan2009-11-221-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89586 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert a few tests to FileCheck for PR5307.Edward O'Callaghan2009-11-224-6/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89584 91177308-0d34-0410-b5e6-96231b3b80d8
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