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* Flip the new block-placement pass to be on by default.Chandler Carruth2012-04-161-1/+1
* 1. Remove the part of r153848 which optimizes shuffle-of-shuffle into a newNadav Rotem2012-04-071-1/+1
* This commit contains a few changes that had to go in together.Nadav Rotem2012-04-011-1/+1
* Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnuEli Bendersky2012-03-251-8/+1
* Replace all instances of dg.exp file with lit.local.cfg, since all tests are ...Eli Bendersky2012-02-162-5/+13
* This patch addresses the problem of poor code generation for the zextNadav Rotem2012-02-121-1/+1
* Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem2012-01-171-2/+2
* Remove histogram tests.Jakob Stoklund Olesen2011-11-122-56/+0
* Reapply r143206, with fixes. Disallow physical register lifetimesDan Gohman2011-11-036-0/+19
* Revert r143206, as there are still some failing tests.Dan Gohman2011-10-296-19/+0
* Reapply r143177 and r143179 (reverting r143188), with schedulerDan Gohman2011-10-286-0/+19
* Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands2011-10-286-19/+0
* Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman2011-10-286-0/+19
* Enable element promotion type legalization by deafault.Nadav Rotem2011-10-163-27/+13
* Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there wasNadav Rotem2011-10-161-0/+4
* Mark 'branch indirect' instruction as an indirect branch.Kalle Raiskila2011-10-131-6/+6
* Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.Kalle Raiskila2011-09-021-1/+12
* make the asmparser reject function and type redefinitions. 'Merging' hasn't ...Chris Lattner2011-06-171-3/+0
* manually upgrade a bunch of tests to modern syntax, and remove some thatChris Lattner2011-06-177-61/+61
* don't test for codegen of 'store undef'Chris Lattner2011-04-091-4/+8
* Roll r127459 back in:Cameron Zwarich2011-03-111-1/+1
* Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often getDaniel Dunbar2011-03-111-1/+1
* Optimize trivial branches in CodeGenPrepare, which often get created from theCameron Zwarich2011-03-111-1/+1
* Fix mistyped CHECK lines.Benjamin Kramer2011-03-091-3/+3
* Be nice to Xcore and the XMOS assembler and avoid quoting section namesJoerg Sonnenberger2011-03-041-1/+1
* Allow vector shifts (shl,lshr,ashr) on SPU.Kalle Raiskila2011-03-041-6/+55
* Allow load from constant on SPU.Kalle Raiskila2011-03-042-0/+15
* Bug#9033: For the ELF assembler output, always quote the section name.Joerg Sonnenberger2011-03-031-1/+1
* fix visitShift to properly zero extend the shift amount if the provided operandChris Lattner2011-02-131-1/+1
* Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila2011-01-201-0/+21
* Don't crash SPU BE with memory accesses with big alignmnet.Kalle Raiskila2011-01-171-0/+9
* Don't feed 19 bit immediates to ILA.Kalle Raiskila2010-12-171-2/+13
* If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG messag...Devang Patel2010-12-061-24/+19
* Handle lshr for i128 correctly on SPU also when Kalle Raiskila2010-11-291-2/+14
* Enable PostRA scheduling for SPU. Kalle Raiskila2010-11-292-4/+4
* Allow for 'fcmp ogt' in SPU.Kalle Raiskila2010-11-241-6/+19
* Division by pow-of-2 is not cheap on SPU, do it with Kalle Raiskila2010-11-231-0/+22
* Fix a bug with extractelement on SPU.Kalle Raiskila2010-11-221-1/+13
* Fix memory access lowering on SPU, addingKalle Raiskila2010-11-123-1/+26
* Change v64 datalayout in SPU.Kalle Raiskila2010-10-262-2/+15
* Improve lowering of sext to i128 on SPU.Kalle Raiskila2010-10-181-0/+3
* Zap some redundant 'ori $?, $?, 0' from SPU.Kalle Raiskila2010-10-011-0/+1
* Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.Kalle Raiskila2010-09-161-3/+2
* Fix CellSPU vector shuffles, again.Kalle Raiskila2010-09-081-0/+26
* Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila2010-08-291-0/+8
* Fix SPU BE to use all the available return registers.Kalle Raiskila2010-08-241-2/+24
* Fix a bug with insertelement on SPU. Kalle Raiskila2010-08-181-0/+15
* Remove all traces of v2[i,f]32 on SPU. Kalle Raiskila2010-08-183-10/+10
* Change SPU C calling convention to match that described in Kalle Raiskila2010-08-181-0/+33
* Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila2010-08-092-3/+15