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* Make nomips16 mask not repeat if it ends with a '.'.Reed Kotler2013-09-231-0/+19
| | | | | | | | This mask is purely for debugging and testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191231 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. ↵Daniel Sanders2013-09-231-0/+113
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191203 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching insert and copy from normal IR (i.e. ↵Daniel Sanders2013-09-231-0/+226
| | | | | | | | | | | | not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-231-0/+60
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191198 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-231-0/+68
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191195 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching and, or, and xor from normal IR (i.e. ↵Daniel Sanders2013-09-232-0/+390
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191194 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented build_vector using ldi, fill, and custom ↵Daniel Sanders2013-09-232-0/+177
| | | | | | | | | | | | | | | | | | | SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
* Set .reorder for the stub so that gas takes care of delay slot processing.Reed Kotler2013-09-211-0/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191125 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two issues regarding Got pointer (GP) setup.Reed Kotler2013-09-181-10/+12
| | | | | | | | | | | | | | | | | 1) make sure that the first two instructions of the sequence cannot separate from each other. The linker requires that they be sequential. If they get separated, it can still work but it will not work in all cases because the first of the instructions mostly involves the hi part of the pc relative offset and that part changes slowly. You would have to be at the right boundary for this to matter. 2) make sure that this sequence begins on a longword boundary. There appears to be a bug in binutils which makes some of these calculations get messed up if the instruction sequence does not begin on a longword boundary. This is being investigated with the appropriate binutils folks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190966 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand the mask capability for deciding which functions are mips16 and mips32Reed Kotler2013-09-151-0/+73
| | | | | | | | | so it can be better used for general interoperability testing between mips32 and mips16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190762 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added test cases that were supposed to be part of r190507, ↵Daniel Sanders2013-09-113-0/+734
| | | | | | r190509, r190512, and r190518. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190522 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv ↵Daniel Sanders2013-09-112-0/+323
| | | | | | from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190518 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, ↵Daniel Sanders2013-09-112-0/+224
| | | | | | fsqrt, and fsub from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190512 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching div_[su] from normal IR (i.e. not ↵Daniel Sanders2013-09-111-0/+130
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190509 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-111-0/+68
| | | | | | | | The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190507 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsicsDaniel Sanders2013-09-111-52/+86
| | | | | | | | | The elements of the operands should be half the width of the elements of the result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190505 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Removed unsupported dot product instructions (dotp_[su].b)Daniel Sanders2013-09-101-44/+0
| | | | | | | | The dotp_[su].b instructions never existed in any revision of the MSA spec. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190398 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix typos.Akira Hatanaka2013-09-071-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190236 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index doubleAkira Hatanaka2013-09-071-15/+63
| | | | | | | | | | | precision loads and stores as well as reg+imm double precision loads and stores. Previously, expansion of loads and stores was done after register allocation, but now it takes place during legalization. As a result, users will see double precision stores and loads being emitted to spill and restore 64-bit FP registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Set instruction itineraries of loads, stores and conditional moves.Akira Hatanaka2013-09-061-16/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we don't generate stubs for any of these functions because theyReed Kotler2013-09-011-15/+13
| | | | | | | | | | | don't exist in libc. This is really not the right way to solve this problem; but it's not clear to me at this time exactly what is the right way. If we create stubs here, they will cause link errors because these functions do not exist in libc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189727 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a problem with dual mips16/mips32 mode. When the underlying processorReed Kotler2013-08-301-0/+38
| | | | | | | | | | | | | | | has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189690 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.vDaniel Sanders2013-08-282-0/+134
| | | | | | | | | | | | | | | These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added load/store intrinsics.Daniel Sanders2013-08-282-0/+298
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189476 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added move.vDaniel Sanders2013-08-281-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189471 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added cfcmsa, and ctcmsaDaniel Sanders2013-08-281-0/+167
| | | | | | | | | The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ↵Daniel Sanders2013-08-284-0/+976
| | | | | | ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189467 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Summarize testsDaniel Sanders2013-08-2840-4/+114
| | | | | | | Adds a comment to the start of each test summarizing the area the test covers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189465 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added tests for and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v ↵Daniel Sanders2013-08-271-43/+523
| | | | | | | | | | | | | when non-byte vectors are used. Note that all of these tests use ld.b and st.b for the loads and stores regardless of the data size. This is because the definition of bitcast is equivalent to a store/load sequence and DAG combiner accordingly folds bitcasts to/from v16i8 into the load/store nodes to product load/store nodes with type v16i8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189333 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added spill/reload supportDaniel Sanders2013-08-271-0/+597
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189332 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added bitconverts for vector types for big and little-endianDaniel Sanders2013-08-271-0/+1208
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189330 91177308-0d34-0410-b5e6-96231b3b80d8
* Start to add the LLVM builtins to the mips16 exclusion lists for fp.Reed Kotler2013-08-251-0/+28
| | | | | | | | | | | | | | | | I need to add the rest of these to the list or else to delay putting out the actual stub until later in code generation when I know if the external function ever got emitted Resubmit this patch. The target triple needs to be added to the test so that clang does not tell the backend the wrong target when the host is BSD. There is a clang bug in here somewhere that I need to track down. At Mips this has been filed internally as a bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189186 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 189161Shuxin Yang2013-08-241-28/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189176 91177308-0d34-0410-b5e6-96231b3b80d8
* Start to add the builtind to the mips16 exclusion lists for fp.Reed Kotler2013-08-241-0/+28
| | | | | | | | | | I need to add the rest of these to the list or else to delay putting out the actual stub until later in code generation when I know if the external function ever got emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189161 91177308-0d34-0410-b5e6-96231b3b80d8
* Update to remove the no-frame-pointer-elim-non-leaf flag if it was set to ↵Bill Wendling2013-08-2219-42/+42
| | | | | | 'false'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189068 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: remove !tbaa from testing cases when they are not needed.Manman Ren2013-08-212-204/+192
| | | | | | | | This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188944 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add support for mfhc1 and mthc1.Akira Hatanaka2013-08-201-6/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an option which permits the user to specify using a bitmask, that variousReed Kotler2013-08-201-0/+23
| | | | | | | | | | | functions be compiled as mips32, without having to add attributes. This is useful in certain situations where you don't want to have to edit the function attributes in the source. For now it's only an option used for the compiler developers when debugging the mips16 port. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188826 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Removed fcge, fcgt, fsge, fsgtDaniel Sanders2013-08-201-176/+0
| | | | | | | | | These instructions were present in a draft spec but were removed before publication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188782 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added insveDaniel Sanders2013-08-201-0/+91
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188777 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.vDaniel Sanders2013-08-201-0/+176
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a subtle difference between running clang vs llc for mips16.Reed Kotler2013-08-161-0/+27
| | | | | | | | | | | | | | | | | | This regards how mips16 is viewed. It's not really a target type but there has always been a target for it in the td files. It's more properly -mcpu=mips32 -mattr=+mips16 . This is how clang treats it but we have always had the -mcpu=mips16 which I probably should delete now but it will require updating all the .ll test cases for mips16. In this case it changed how we decide if we have a count bits instruction and whether instruction lowering should then expand ctlz. Now that we have dual mode compilation, -mattr=+mips16 really just indicates the inital processor mode that we are compiling for. (It is also possible to have -mcpu=64 -mattr=+mips16 but as far as I know, nobody has even built such a processor, though there is an architecture manual for this). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188586 91177308-0d34-0410-b5e6-96231b3b80d8
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-161-2/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188513 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips][msa] Added the simple builtins (madd_q to xori)Jack Carter2013-08-1514-0/+3692
| | | | | | | | | | | | | Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188460 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips][msa] Added the simple builtins (fadd to ftq)Jack Carter2013-08-1511-0/+1710
| | | | | | | | | | | | | Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188458 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)Jack Carter2013-08-1513-0/+4027
| | | | | | | | | | | | | | Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Properly parse registers that appear in inline-asm constraints.Akira Hatanaka2013-08-141-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188336 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't generate floating point stubs for mips16 code if the functionReed Kotler2013-08-111-0/+25
| | | | | | | | | | | | | is actually an instrinsic that will not occur in libc. This list here is not exhaustive but fixes the one places in test-suite where this occurs. I have filed a bug against myself to research the full list and add them to the array of such cases. In the future, actual stub generation will occur in a later phase and we won't need this code because we will know at that time during the compilation that in fact no helper function was even needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188149 91177308-0d34-0410-b5e6-96231b3b80d8
* Add another intrinsic that LLVM gives an incorrect prototype to.Reed Kotler2013-08-091-0/+18
| | | | | | | | | | I need to go through all the runtime routine list and see if there are any more I need to add for mips16 floating point. Prototypes must be correct or else I don't know to add a helper function call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188106 91177308-0d34-0410-b5e6-96231b3b80d8
* Create a pattern for the "trap" instruction.Reed Kotler2013-08-071-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187863 91177308-0d34-0410-b5e6-96231b3b80d8
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