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* Update aosp/master LLVM with patches for fp16Pirama Arumuga Nainar2015-05-261-0/+98
| | | | | | | | | | Cherry-pick LLVM revisions r235191, r235215, r235220, r235341, r235363, r235530, r235609, r235610, r237004 r235191 has a required bug-fix and the rest are all related to fp16. Change-Id: I7fe8da5ffd8f2c06150885a54769abd18c3a04c6 (cherry picked from commit a18e6af1712fd41c4a705a19ad71f6e9ac7a4e68)
* Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar2015-05-1852-144/+241
| | | | | Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7 (cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-09305-4314/+5510
| | | | Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-23102-399/+4239
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-0272-451/+4220
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Add support for scalarizing cttz_zero_undefPetar Jovanovic2014-08-261-0/+37
| | | | | | | | | Follow up to r214266. Add missing case in ScalarizeVectorResult() for cttz_zero_undef. Differential Revision: http://reviews.llvm.org/D4813 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215330 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for scalarizing ctlz_zero_undefPetar Jovanovic2014-08-261-0/+19
| | | | | | | | | Fix the missing case in ScalarizeVectorResult() that was exposed with libclcore.bc in Android. Differential Revision: http://reviews.llvm.org/D4645 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214266 91177308-0d34-0410-b5e6-96231b3b80d8
* Update LLVM for rebase to r212749.Stephen Hines2014-07-2146-1017/+5166
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-2969-16716/+2983
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-24103-613/+19183
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Merged r195973:Daniel Sanders2013-12-011-0/+85
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195973 | dsanders | 2013-11-30 13:47:57 +0000 (Sat, 30 Nov 2013) | 5 lines [mips][msa] MSA loads and stores have a 10-bit offset. Account for this when lowering FrameIndex. This prevents the compiler from emitting invalid ld.[bhwd]'s and st.[bhwd]'s when the stack frame is between 512 and 32,768 bytes in size. ------------------------------------------------------------------------ Review of this commit by Matheus Almeida revealed that it is still possible to emit invalid code (when the offset is not a multiple of the element size). However, we agreed that this commit still represents an improvement since it fixes many cases that previously emitted invalid code, and does not cause any cases that previously emitted valid code to emit invalid code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196049 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195469:Bill Wendling2013-11-261-0/+31
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r195469 | dsanders | 2013-11-22 07:47:18 -0800 (Fri, 22 Nov 2013) | 4 lines [mips][msa] Add test case that should have been added in r195456. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195744 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195444:Bill Wendling2013-11-261-0/+27
| | | | | | | | | | | | | | ------------------------------------------------------------------------ r195444 | dsanders | 2013-11-22 03:24:50 -0800 (Fri, 22 Nov 2013) | 4 lines [mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from the appropriate integer vector type. Fixes an instruction selection failure detected by llvm-stress. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195742 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195364:Bill Wendling2013-11-261-0/+33
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195364 | dsanders | 2013-11-21 08:11:31 -0800 (Thu, 21 Nov 2013) | 12 lines [mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT. Mask == ~InvMask asserts if the width of Mask and InvMask differ. The combine isn't valid (with two exceptions, see below) if the widths differ so test for this before testing Mask == ~InvMask. In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and InvMask=~0, the combine is still valid. However, there are more appropriate combines that could be used in these cases such as folding x & 0 to 0, or x & ~0 to x. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195741 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195343:Bill Wendling2013-11-261-0/+141
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195343 | dsanders | 2013-11-21 03:40:14 -0800 (Thu, 21 Nov 2013) | 5 lines [mips][msa/dsp] Only do DSP combines if DSP is enabled. Fixes a crash (null pointer dereferenced) when MSA is enabled. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195740 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195635:Daniel Sanders2013-11-251-0/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195635 | dsanders | 2013-11-25 11:14:43 +0000 (Mon, 25 Nov 2013) | 19 lines Fixed tryFoldToZero() for vector types that need expansion. Summary: Moved the requirement for SelectionDAG::getConstant() to return legally typed nodes slightly earlier. There were two optional DAGCombine passes that were missed out and were required to produce type-legal DAGs. Simplified a code-path in tryFoldToZero() to use SelectionDAG::getConstant(). This provides support for both promoted and expanded vector types whereas the previous code only supported promoted vector types. Fixes a "Type for zero vector elements is not legal" assertion detected by an llvm-stress generated test. Reviewers: resistor CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2251 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195651 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r195355:Daniel Sanders2013-11-212-0/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195355 | dsanders | 2013-11-21 13:24:49 +0000 (Thu, 21 Nov 2013) | 20 lines Add support for legalizing SETNE/SETEQ by inverting the condition code and the result of the comparison. Summary: LegalizeSetCCCondCode can now legalize SETEQ and SETNE by returning the inverse condition and requesting that the caller invert the result of the condition. The caller of LegalizeSetCCCondCode must handle the inverted CC, and they do so as follows: SETCC, BR_CC: Invert the result of the SETCC with SelectionDAG::getNOT() SELECT_CC: Swap the true/false operands. This is necessary for MSA which lacks an integer SETNE instruction. Reviewers: resistor CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2229 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195363 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code ↵Daniel Sanders2013-11-181-0/+31
| | | | | | | | | | | | for (ConstantFP 0.0) Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64 which resulted in an impossible constraint on the register allocation. It now uses BuildPairF64_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Merge basic_operations_little.ll into basic_operations.ll.Daniel Sanders2013-11-152-639/+184
| | | | | | | | | Now that FileCheck supports multiple check prefixes, we don't need to keep the little and big endian versions of this test separate anymore. Merge them back together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194826 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 typeDaniel Sanders2013-11-159-26/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When getConstant() is called for an expanded vector type, it is split into multiple scalar constants which are then combined using appropriate build_vector and bitcast operations. In addition to the usual big/little endian differences, the case where the element-order of the vector does not have the same endianness as the elements themselves is also accounted for. For example, for v4i32 on big-endian MIPS, the byte-order of the vector is <3210,7654,BA98,FEDC>. For little-endian, it is <0123,4567,89AB,CDEF>. Handling this case turns out to be a nop since getConstant() returns a splatted vector (so reversing the element order doesn't change the value) This fixes a number of cases in MIPS MSA where calling getConstant() during operation legalization introduces illegal types (e.g. to legalize v2i64 UNDEF into a v2i64 BUILD_VECTOR of illegal i64 zeros). It should also handle bigger differences between illegal and legal types such as legalizing v2i64 into v8i16. lowerMSASplatImm() in the MIPS backend no longer needs to avoid calling getConstant() so this function has been updated in the same patch. For the sake of transparency, the steps I've taken since the review are: * Added 'virtual' to isVectorEltOrderLittleEndian() as requested. This revealed that the MIPS tests were falsely passing because a polymorphic function was not actually polymorphic in the reviewed patch. * Fixed the tests that were now failing. This involved deleting the code to handle the MIPS MSA element-order (which was previously doing an byte-order swap instead of an element-order swap). This left isVectorEltOrderLittleEndian() unused and it was deleted. * Fixed build failures caused by rebasing beyond r194467-r194472. These build failures involved the bset, bneg, and bclr instructions added in these commits using lowerMSASplatImm() in a way that was no longer valid after this patch. Some of these were fixed by calling SelectionDAG::getConstant() instead, others were fixed by a new function getBuildVectorSplat() that provided the removed functionality of lowerMSASplatImm() in a more sensible way. Reviewers: bkramer Reviewed By: bkramer CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1973 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194811 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Build all the tests in little and big endian modes and correct ↵Daniel Sanders2013-11-1559-3/+666
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | an incorrect test. Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
* Make all the conditional Mips 16 branches get initially set for theReed Kotler2013-11-154-0/+86
| | | | | | | | | | | | short form. Constant islands will expand them if they are out of range. Since there is not direct object emitter at this time, it does not have any material affect because the assembler sorts this out. But we need to know for the actual constant island work. We track the difference by putting # 16 inst in the comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194766 91177308-0d34-0410-b5e6-96231b3b80d8
* Take care of long short branch immediate instructions for mips16 inReed Kotler2013-11-132-0/+59
| | | | | | | | constant islands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194630 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the code which returns the length for inline assembler to knowReed Kotler2013-11-131-0/+29
| | | | | | | | | | | specifically about the .space directive. This allows us to force large blocks of code to appear in test cases for things like constant islands without having to make giant test cases to force things like long branches to take effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194555 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix a bug in function CC_MipsO32_FP64. The second double precisionAkira Hatanaka2013-11-121-6/+6
| | | | | | | | argument was not being passed in $f14. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194522 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Run test case with command line option -mattr=+fp64.Akira Hatanaka2013-11-121-16/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194519 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix and re-enable a test case that has been disabled for a long time.Akira Hatanaka2013-11-121-99/+120
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194510 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Enable inlinse assembly for MSA.Daniel Sanders2013-11-121-0/+34
| | | | | | | | | | | | | | | | Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194476 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. ↵Daniel Sanders2013-11-122-1/+139
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from ↵Daniel Sanders2013-11-121-0/+248
| | | | | | normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194469 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Change constant used in ori tests to avoid conflict with bseti ↵Daniel Sanders2013-11-121-16/+16
| | | | | | | | | | | | | | (also xori to avoid bnegi) Upcoming commit(s) are going to add support for bseti and bnegi. This would cause some existing tests to (correctly) change behaviour and emit a different instruction. This patch prevents this by changing the constant used in ori and xori tests so that they will not be matchable by the bseti and bnegi patterns when these instructions are matchable from normal IR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194467 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the default branch instruction to be the 16 bit variety for mips16.Reed Kotler2013-11-121-0/+37
| | | | | | | | | | | | | This has no material effect at this time since we don't have a direct object emitter for mips16 and the assembler can't tell them apart. I place a comment "16 bit inst" for those so that I can tell them apart in the output. The constant island pass has only been minimally changed to allow this. More complete branch work is forthcoming but this is the first step. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194442 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Partially revert r193641. Stack alignment should not be determined byAkira Hatanaka2013-11-111-2/+1
| | | | | | | | the floating point register mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194423 91177308-0d34-0410-b5e6-96231b3b80d8
* Vector forms of SHL, SRA, and SRL can be constant folded using ↵Daniel Sanders2013-11-111-0/+70
| | | | | | | | | | | | | | SimplifyVBinOp too Reviewers: dsanders Reviewed By: dsanders CC: llvm-commits, nadav Differential Revision: http://llvm-reviews.chandlerc.com/D1958 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194393 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 3r-a.ll test.Matheus Almeida2013-11-111-192/+336
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194391 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 2rf_int_float.ll test.Matheus Almeida2013-11-111-30/+50
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194390 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 2rf_float_int.ll test.Matheus Almeida2013-11-111-12/+20
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194389 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 2rf.ll test.Matheus Almeida2013-11-111-48/+80
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194387 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 2r.ll test.Matheus Almeida2013-11-111-36/+60
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194386 91177308-0d34-0410-b5e6-96231b3b80d8
* Mostly finish up constant islands port for Mips for load constants.Reed Kotler2013-11-103-64/+344
| | | | | | | | | Still need to finish the branch part. Still lots more review of the code, clean up and testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194337 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Make sure there is a chain edge dependency between loads that readAkira Hatanaka2013-11-092-7/+20
| | | | | | | | | | formal arguments on the stack and stores created afterwards. We need this to ensure tail call optimized function calls do not write over the argument area of the stack before it is read out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194309 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix r194019 as requested by Eric Christopher.Reed Kotler2013-11-051-0/+64
| | | | | | | | | | | | | | | | | | | | | | | Submit the basic port of the rest of ARM constant islands code to Mips. Two test cases are added which reflect the next level of functionality: constants getting moved to water areas that are out of range from the initial placement at the end of the function and basic blocks being split to create water when none exists that can be used. There is a bunch of this code that is not complete and has been marked with IN_PROGRESS. I will finish cleaning this all up during the next week or two and submit the rest of the test cases. I have elminated some code for dealing with inline assembly because to me it unecessarily complicates things and some of the newer features of llvm like function attributies and builtin assembler give me better tools to solve the alignment issues created there. Also, for Mips16 I even have the option of not doing constant islands in the present of inline assembler if I chose. When everything has been completed I will summarize the port and notify people that are knowledgable regarding the ARM Constant Islands code so they can review it in it's entirety if they wish. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194053 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r194019 to r194021, "Submit the basic port of the rest of ARM ↵NAKAMURA Takumi2013-11-041-64/+0
| | | | | | | | constant islands code to Mips." It broke -Asserts build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194026 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the test case that goes with the previous submission for constant Reed Kotler2013-11-041-0/+64
| | | | | | | | islands. I forgot to add it to svn on that patch. Ooops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194020 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related testsDaniel Sanders2013-10-301-73/+121
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193695 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from ↵Daniel Sanders2013-10-304-162/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193693 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. ↵Daniel Sanders2013-10-302-84/+216
| | | | | | | | | | | | | | | | | | | not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Combine binsri-like DAG of AND and OR into equivalent VSELECTDaniel Sanders2013-10-301-0/+164
| | | | | | | | | | | | | | | | | (or (and $a, $mask), (and $b, $inverse_mask)) => (vselect $mask, $a, $b). where $mask is a constant splat. This allows bitwise operations to make use of bsel. It's also a stepping stone towards matching bins[lr], and bins[lr]i from normal IR. Two sets of similar tests have been added in this commit. The bsel_* functions test the case where binsri cannot be used. The binsr_*_i functions will start to use the binsri instruction in the next commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193682 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not ↵Daniel Sanders2013-10-301-33/+44
| | | | | | | | | | | intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193680 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Align the stack to 16-bytes for mfp64.Akira Hatanaka2013-10-291-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193641 91177308-0d34-0410-b5e6-96231b3b80d8
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