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* Have getRegForInlineAsmConstraint return the correct register class when targetAkira Hatanaka2012-01-042-0/+55
| | | | | | | | is Mips64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147516 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r147232.Akira Hatanaka2011-12-241-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147233 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in zero-store peephole pattern reported in pr11615.Akira Hatanaka2011-12-211-0/+19
| | | | | | | | The patch and test case were originally written by Mans Rullgard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand 64-bit CTLZ nodes if target architecture does not support it. Add testAkira Hatanaka2011-12-211-0/+19
| | | | | | | case for DCLO and DCLZ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r147017.Akira Hatanaka2011-12-201-0/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147018 91177308-0d34-0410-b5e6-96231b3b80d8
* Add function MipsDAGToDAGISel::SelectMULT and factor out code that generatesAkira Hatanaka2011-12-201-0/+8
| | | | | | | | | nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
* 64-bit data directive.Akira Hatanaka2011-12-201-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8
* 32-to-64-bit sext_inreg pattern.Akira Hatanaka2011-12-201-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
* Add code in MipsDAGToDAGISel for selecting constant +0.0.Akira Hatanaka2011-12-201-0/+7
| | | | | | | MIPS64 can generate constant +0.0 with a single DMTC1 instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for r146900.Akira Hatanaka2011-12-191-0/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146901 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for matching immediates whose lower 16-bit is cleared. TheseAkira Hatanaka2011-12-192-6/+11
| | | | | | | | patterns emit a single LUi instruction instead of a pair of LUi and ORi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove definitions of double word shift plus 32 instructions. Assembler orAkira Hatanaka2011-12-192-6/+6
| | | | | | | | | direct-object emitter should emit the appropriate shift instruction depending on the shift amount. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the restriction on the first operand of the add node in SelectAddr.Akira Hatanaka2011-12-191-1/+1
| | | | | | | | | | | | | | | | | | | | This change reduces the number of instructions generated. For example, (load (add (sub $n0, $n1), (MipsLo got(s)))) results in the following sequence of instructions: 1. sub $n2, $n0, $n1 2. lw got(s)($n2) Previously, three instructions were needed. 1. sub $n2, $n0, $n1 2. addiu $n3, $n2, got(s) 3. lw 0($n3) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct objectAkira Hatanaka2011-12-141-0/+19
| | | | | | | | | emission is not supported yet, but a patch that adds the support should follow soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146572 91177308-0d34-0410-b5e6-96231b3b80d8
* Move direct object emitter test to directory test/MC/Mips. Rename it toAkira Hatanaka2011-12-131-29/+0
| | | | | | | elf-relsym.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146470 91177308-0d34-0410-b5e6-96231b3b80d8
* Relocation against a symbol, instead of against section. We had some extremeAkira Hatanaka2011-12-131-0/+29
| | | | | | | | | | | | test cases where there were a lot of relocations applied relative to a large rodata section. Gas would create a symbol for each of these whereas we would be relative to the beginning of the rodata section. This change mimics what gas does. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146468 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r146432 by Jack Carter.Akira Hatanaka2011-12-121-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146433 91177308-0d34-0410-b5e6-96231b3b80d8
* Manually upgrade the test suite to specify the flag to cttz and ctlz.Chandler Carruth2011-12-123-10/+10
| | | | | | | | | | | | | | | | | | | | | | | I followed three heuristics for deciding whether to set 'true' or 'false': - Everything target independent got 'true' as that is the expected common output of the GCC builtins. - If the target arch only has one way of implementing this operation, set the flag in the way that exercises the most of codegen. For most architectures this is also the likely path from a GCC builtin, with 'true' being set. It will (eventually) require lowering away that difference, and then lowering to the architecture's operation. - Otherwise, set the flag differently dependending on which target operation should be tested. Let me know if anyone has any issue with this pattern or would like specific tests of another form. This should allow the x86 codegen to just iteratively improve as I teach the backend how to differentiate between the two forms, and everything else should remain exactly the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146370 91177308-0d34-0410-b5e6-96231b3b80d8
* jalr should use t9 ($25) for indirect calls regardless of the relocation modelAkira Hatanaka2011-12-091-0/+8
| | | | | | | | specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146229 91177308-0d34-0410-b5e6-96231b3b80d8
* 32 to 64-bit zext pattern.Akira Hatanaka2011-12-071-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146096 91177308-0d34-0410-b5e6-96231b3b80d8
* 64-bit WrapperPICPat patterns.Akira Hatanaka2011-12-071-8/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146086 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify LowerFCOPYSIGN to handle Mips64.Akira Hatanaka2011-12-071-38/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146080 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 64-bit immediate patterns.Akira Hatanaka2011-12-071-0/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146059 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of 64-bit extract and insert instrucions and makeAkira Hatanaka2011-12-051-0/+55
| | | | | | | | | PerformANDCombine and PerformOrCombine aware of them. Test cases are included too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145853 91177308-0d34-0410-b5e6-96231b3b80d8
* Have LowerJumpTable support Mips64. Modify 2010-07-20-Switch.ll to test N64 andAkira Hatanaka2011-12-051-5/+13
| | | | | | | O32 with relocation-model=pic too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145850 91177308-0d34-0410-b5e6-96231b3b80d8
* Test cases for 64-bit multiplication and division.Akira Hatanaka2011-12-021-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145717 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test cases to use FileCheck.Akira Hatanaka2011-12-029-81/+79
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145716 91177308-0d34-0410-b5e6-96231b3b80d8
* Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka2011-11-296-8/+8
| | | | | | | | | | | | tools use. Patch by Simon Atanasyan. "mips32r1" => "mips32" "4ke" => mips32r2" "mips64r1" => "mips64" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145451 91177308-0d34-0410-b5e6-96231b3b80d8
* Upgrade syntax of tests using volatile instructions to use 'load volatile' ↵Chris Lattner2011-11-272-3/+3
| | | | | | instead of 'volatile load', which is archaic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r143206, with fixes. Disallow physical register lifetimesDan Gohman2011-11-032-10/+2
| | | | | | | | across calls, and only check for nested dependences on the special call-sequence-resource register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143660 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r143206, as there are still some failing tests.Dan Gohman2011-10-292-2/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143262 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r143177 and r143179 (reverting r143188), with schedulerDan Gohman2011-10-282-10/+2
| | | | | | | | | | fixes: Use a separate register, instead of SP, as the calling-convention resource, to avoid spurious conflicts with actual uses of SP. Also, fix unscheduling of calling sequences, which can be triggered by pseudo-two-address dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143206 91177308-0d34-0410-b5e6-96231b3b80d8
* Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands2011-10-282-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | it fixes the dragonegg self-host (it looks like gcc is miscompiled). Original commit messages: Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. Delete #if 0 code accidentally left in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143188 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman2011-10-282-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143177 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the default scheduler from Latency to ILP, since LatencyDan Gohman2011-10-249-81/+59
| | | | | | | is going away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142810 91177308-0d34-0410-b5e6-96231b3b80d8
* Test cases for 64-bit load and store instructions.Akira Hatanaka2011-10-112-0/+215
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141631 91177308-0d34-0410-b5e6-96231b3b80d8
* Move CHECK after entry label.Akira Hatanaka2011-10-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141030 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 64-bit logical NOR.Akira Hatanaka2011-10-031-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 64-bit count leading ones and zeros instructions.Akira Hatanaka2011-10-031-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141028 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 64-bit divide instructions.Akira Hatanaka2011-10-031-0/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141024 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 64-bit integer multiply instructions.Akira Hatanaka2011-10-031-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141017 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary checking of register operands.Akira Hatanaka2011-09-302-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140872 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of Mips64 rotate instructions.Akira Hatanaka2011-09-301-1/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140870 91177308-0d34-0410-b5e6-96231b3b80d8
* Check values of immediate operands.Akira Hatanaka2011-09-302-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140860 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips64 shift instructions.Akira Hatanaka2011-09-301-0/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140841 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips64 arithmetic and logical instructions with one source register andAkira Hatanaka2011-09-301-0/+36
| | | | | | | immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140839 91177308-0d34-0410-b5e6-96231b3b80d8
* Fill delay slot with useful instructions. Modified from Sparc's version of delayAkira Hatanaka2011-09-291-0/+15
| | | | | | | | | slot filler. Patch by Reed Kotler at Mips Technologies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140825 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips64 arithmetic and logical instructions with two source registers.Akira Hatanaka2011-09-291-0/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140806 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more tests over to the new atomic instructions.Eli Friedman2011-09-261-26/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140559 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove +.Akira Hatanaka2011-09-211-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140266 91177308-0d34-0410-b5e6-96231b3b80d8
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