| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Update LLVM for 3.5 rebase (r209712). | Stephen Hines | 2014-05-29 | 1 | -1/+12 |
| * | Update to LLVM 3.5a. | Stephen Hines | 2014-04-24 | 1 | -7/+7 |
| * | R600/SI: Prefer SALU instructions for bit shift operations | Tom Stellard | 2013-11-13 | 1 | -7/+25 |
| * | R600/SI: Change formatting of printed registers. | Matt Arsenault | 2013-11-12 | 1 | -4/+4 |
| * | R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32 | Tom Stellard | 2013-10-23 | 1 | -5/+10 |
| * | R600: Non vector only instruction can be scheduled on trans unit | Vincent Lejeune | 2013-09-04 | 1 | -1/+1 |
| * | Revert "R600: Non vector only instruction can be scheduled on trans unit" | Tom Stellard | 2013-07-31 | 1 | -1/+1 |
| * | R600: Non vector only instruction can be scheduled on trans unit | Vincent Lejeune | 2013-07-31 | 1 | -1/+1 |
| * | DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free | Tom Stellard | 2013-07-23 | 1 | -9/+21 |
| * | R600: Expand vector FNEG | Tom Stellard | 2013-07-23 | 1 | -0/+26 |
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