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* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-8/+8
| | | | Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-29/+30
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-15/+15
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-101-1/+1
| | | | | | | | | | | We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-281-2/+2
| | | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-041-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-311-12/+12
| | | | | | This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-311-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix crash with VSELECTTom Stellard2013-07-181-0/+15
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=66175 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186616 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand VSELECT for all typesTom Stellard2013-07-181-0/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186613 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add v2i32 test for vselectAaron Watry2013-06-251-6/+20
| | | | | | | | | | | | | | Note: Only adding test for evergreen, not SI yet. When I attempted to expand vselect for SI, I got the following: llc: /home/awatry/src/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:522: llvm::SDValue llvm::DAGTypeLegalizer::PromoteIntRes_SETCC(llvm::SDNode*): Assertion `SVT.isVector() == N->getOperand(0).getValueType().isVector() && "Vector compare must return a vector result!"' failed. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184847 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: use capital letter for PV channelVincent Lejeune2013-06-031-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-171-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand vselect for v4i32 and v2i32Tom Stellard2013-05-101-0/+17
v2: Add vselect v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181576 91177308-0d34-0410-b5e6-96231b3b80d8
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