external_llvm.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	R600: Add local memory support via LDS	Tom Stellard	2013-06-28	1	-0/+82
*	R600: Add support for GROUP_BARRIER instruction	Tom Stellard	2013-06-28	1	-0/+24
*	R600: Remove alu-split.ll test	Tom Stellard	2013-06-27	1	-851/+0
*	R600: Use new getNamedOperandIdx function generated by TableGen	Tom Stellard	2013-06-25	1	-0/+59
*	R600: Add v2i32 test for vselect	Aaron Watry	2013-06-25	1	-6/+20
*	R600/SI: Expand xor v2i32/v4i32	Aaron Watry	2013-06-25	1	-7/+33
*	R600: Add v2i32 test for setcc on evergreen	Aaron Watry	2013-06-25	1	-3/+22
*	R600/SI: Expand urem of v2i32/v4i32 for SI	Aaron Watry	2013-06-25	1	-4/+23
*	R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG	Aaron Watry	2013-06-25	1	-3/+22
*	R600/SI: Expand ashr of v2i32/v4i32 for SI	Aaron Watry	2013-06-25	1	-7/+34
*	R600/SI: Expand srl of v2i32/v4i32 for SI	Aaron Watry	2013-06-25	1	-7/+35
*	R600/SI: Expand shl of v2i32/v4i32 for SI	Aaron Watry	2013-06-25	1	-7/+34
*	R600/SI: Expand or of v2i32/v4i32 for SI	Aaron Watry	2013-06-25	1	-7/+34
*	R600/SI: Expand mul of v2i32/v4i32 for SI	Aaron Watry	2013-06-25	1	-6/+32
*	R600/SI: Expand and of v2i32/v4i32 for SI	Aaron Watry	2013-06-25	1	-6/+31
*	R600/SI: Report unaligned memory accesses as legal for > 32-bit types	Tom Stellard	2013-06-25	1	-0/+32
*	R600: Add support for i32 loads from the constant address space on Cayman	Tom Stellard	2013-06-25	1	-0/+1
*	R600/SI: Add support for v4i32 and v4f32 kernel args	Tom Stellard	2013-06-25	1	-6/+10
*	R600: Fix typo in R600Schedule.td	Tom Stellard	2013-06-25	1	-0/+34
*	R600/SI: Expand sub for v2i32 and v4i32 for SI	Tom Stellard	2013-06-20	1	-6/+31
*	R600/SI: Expand add for v2i32 and v4i32	Tom Stellard	2013-06-20	1	-6/+31
*	R600: Expand v2i32 load/store instead of custom lowering	Tom Stellard	2013-06-20	1	-0/+6
*	R600: PV stores Reg id, not index	Vincent Lejeune	2013-06-17	1	-0/+50
*	R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.	Vincent Lejeune	2013-06-17	1	-0/+44
*	R600: Add SI load support for v[24]i32 and store for v2i32	Tom Stellard	2013-06-15	1	-0/+19
*	R600: Use correct encoding for Vertex Fetch instructions on Cayman	Tom Stellard	2013-06-14	1	-0/+25
*	R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman	Tom Stellard	2013-06-14	1	-0/+3
*	R600: Anti dep better handled in tex clause	Vincent Lejeune	2013-06-07	1	-0/+24
*	R600: Fix calculation of stack offset in AMDGPUFrameLowering	Tom Stellard	2013-06-07	1	-0/+33
*	R600: Fix the fetch limits for R600 generation GPUs	Tom Stellard	2013-06-07	2	-0/+129
*	R600: Add a pass that merge Vector Register	Vincent Lejeune	2013-06-05	1	-0/+30
*	R600: Schedule copy from phys register at beginning of block	Vincent Lejeune	2013-06-05	10	-10/+10
*	R600: Make sure to schedule AR register uses and defs in the same clause	Tom Stellard	2013-06-05	1	-0/+32
*	Revert "R600: Add a pass that merge Vector Register"	Rafael Espindola	2013-06-05	1	-30/+0
*	R600: Add a pass that merge Vector Register	Vincent Lejeune	2013-06-04	1	-0/+30
*	R600: Const/Neg/Abs can be folded to dot4	Vincent Lejeune	2013-06-04	1	-0/+27
*	R600: Swizzle texture/export instructions	Vincent Lejeune	2013-06-04	1	-5/+5
*	R600: Add a test for r183108	Vincent Lejeune	2013-06-04	1	-0/+2
*	R600/SI: Add support for work item and work group intrinsics	Tom Stellard	2013-06-03	1	-0/+211
*	R600/SI: Add a calling convention for compute shaders	Tom Stellard	2013-06-03	7	-10/+10
*	R600/SI: Custom lower i64 sign_extend	Tom Stellard	2013-06-03	1	-0/+12
*	R600/SI: Add support for global loads	Tom Stellard	2013-06-03	1	-3/+49
*	R600: use capital letter for PV channel	Vincent Lejeune	2013-06-03	14	-17/+17
*	R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg	Tom Stellard	2013-05-23	1	-0/+22
*	R600: Fix rotr.ll on non-asserts builds	Tom Stellard	2013-05-20	1	-6/+2
*	R600/SI: Add pattern for rotr	Tom Stellard	2013-05-20	1	-9/+19
*	R600: Swap the legality of rotl and rotr	Tom Stellard	2013-05-20	1	-0/+29
*	R600/SI: Add patterns for 64-bit shift operations	Tom Stellard	2013-05-20	1	-0/+3
*	R600: Lower int_load_input to copyFromReg instead of Register node	Vincent Lejeune	2013-05-17	1	-0/+121
*	R600: Use bottom up scheduling algorithm	Vincent Lejeune	2013-05-17	15	-17/+19