| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Convert more tests to new atomic instructions. | Eli Friedman | 2011-09-26 | 1 | -13/+1 |
| * | Change some ARM subtarget features to be single bit yes/no in order to sink t... | Evan Cheng | 2011-07-07 | 1 | -1/+1 |
| * | Do not use MEMBARRIER_MCR for any Thumb code. | Bob Wilson | 2010-11-09 | 1 | -0/+1 |
| * | Overhaul memory barriers in the ARM backend. Radar 8601999. | Bob Wilson | 2010-10-30 | 1 | -5/+5 |
| * | Fix test and re-enable it. | Evan Cheng | 2010-08-11 | 1 | -4/+4 |
| * | Temporarily disable some failing tests, until they can be | Dan Gohman | 2010-08-11 | 1 | -2/+2 |
| * | Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) | Evan Cheng | 2010-08-11 | 1 | -6/+6 |
| * | Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit | Evan Cheng | 2010-08-11 | 1 | -5/+12 |
| * | - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the | Evan Cheng | 2010-08-11 | 1 | -0/+17 |
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