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* Enable MI Sched for x86.Andrew Trick2013-10-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Temporarily enable MI-Sched on X86."Andrew Trick2013-06-251-2/+2
| | | | | | This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184823 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily enable MI-Sched on X86.Andrew Trick2013-06-241-2/+2
| | | | | | | Sorry for the unit test churn. I'll try to make the change permanently next time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184705 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-1/+1
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach two-address lowering how to unfold a load to open up commutingDan Gohman2010-06-211-4/+4
| | | | | | | | | | | | | | | | | | | | opportunities. For example, this lets it emit this: movq (%rax), %rcx addq %rdx, %rcx instead of this: movq %rdx, %rcx addq (%rax), %rcx in the case where %rdx has subsequent uses. It's the same number of instructions, and usually the same encoding size on x86, but it appears faster, and in general, it may allow better scheduling for the load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106493 91177308-0d34-0410-b5e6-96231b3b80d8
* Start function numbering at 0.Dan Gohman2010-04-171-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101638 91177308-0d34-0410-b5e6-96231b3b80d8
* Turning off post-ra scheduling for x86. It isn't a consistent win.Evan Cheng2010-03-181-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't enable the post-RA scheduler on x86 except at -O3. In itsDan Gohman2009-12-071-1/+1
| | | | | | | current form, it is too expensive in compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90781 91177308-0d34-0410-b5e6-96231b3b80d8
* Update tests for 84931.Evan Cheng2009-10-231-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84932 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the target to select the level of anti-dependence breaking that should ↵David Goodwin2009-10-221-3/+3
| | | | | | be performed by the post-RA scheduler. The default is none. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn on post-alloc scheduling for x86.Evan Cheng2009-10-181-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84431 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81290 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate some uses of prcontext. Any help here would be appreciated :)Chris Lattner2009-08-301-3/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80520 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman2009-06-041-7/+7
| | | | | | | | | | | | | | | | integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 42908 for now.Evan Cheng2007-10-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42960 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the names used for internal labels to use the currentDan Gohman2007-10-121-1/+1
| | | | | | | | | | function symbol name instead of a codegen-assigned function number. Thanks Evan! :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42908 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert tests using "| wc -l | grep ..." to use the count script.Dan Gohman2007-08-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41097 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the x86 assembly output to use tab characters to separate theDan Gohman2007-07-311-1/+1
| | | | | | | | | | mnemonics from their operands instead of single spaces. This makes the assembly output a little more consistent with various other compilers (f.e. GCC), and slightly easier to read. Also, update the regression tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40648 91177308-0d34-0410-b5e6-96231b3b80d8
* For PR1319: Upgrade to new test harness.Reid Spencer2007-04-151-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36091 91177308-0d34-0410-b5e6-96231b3b80d8
* For PR761:Reid Spencer2007-01-261-1/+1
| | | | | | | | | | | | | | | Remove "target endian/pointersize" or add "target datalayout" to make the test parse properly or set the datalayout because defaults changes. For PR645: Make global names use the @ prefix. For llvm-upgrade changes: Fix test cases or completely remove use of llvm-upgrade for test cases that cannot survive the new renaming or upgrade capabilities. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33533 91177308-0d34-0410-b5e6-96231b3b80d8
* Add PR number for future referenceChris Lattner2007-01-091-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33031 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test case.Evan Cheng2007-01-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33030 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a test case from PR1075.Evan Cheng2007-01-081-0/+13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33028 91177308-0d34-0410-b5e6-96231b3b80d8
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