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* Requires SSE2.Evan Cheng2007-08-011-2/+2
* Change the x86 assembly output to use tab characters to separate theDan Gohman2007-07-3127-43/+43
* Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v...Evan Cheng2007-07-311-0/+16
* Re-apply 40504, but with a fix for the segfault it caused in oggenc:Dan Gohman2007-07-272-1/+15
* Reverting 40504 for now. It's breaking oggenc.Evan Cheng2007-07-271-1/+1
* Test case for PR1573.Evan Cheng2007-07-261-0/+54
* Fix test.Evan Cheng2007-07-261-2/+2
* Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from theDan Gohman2007-07-261-1/+1
* Use movaps to load a v4f32 build_vector of all-constant values into aDan Gohman2007-07-241-0/+5
* Update these regression tests to accomodate X86InstrSSE.td now using movups/m...Dan Gohman2007-07-206-6/+6
* New test.Evan Cheng2007-07-201-0/+42
* New test.Evan Cheng2007-07-191-0/+24
* Try fixing it again.Evan Cheng2007-07-191-1/+1
* For PR1553:Reid Spencer2007-07-195-10/+10
* Don't need the "&&" to glue lines together.Bill Wendling2007-07-191-1/+1
* Testcase for PR1549Bill Wendling2007-07-191-0/+15
* New test.Evan Cheng2007-07-181-0/+11
* Implement initial memory alignment awareness for SSE instructions. Vector loadsDan Gohman2007-07-1811-0/+112
* It's not necessary to do rounding for alloca operations when the requestedDan Gohman2007-07-18226-0/+6557
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