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* Add addrspacecast instruction.Matt Arsenault2013-11-151-4/+4
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-152-3/+104
* Simplify testcase.Eric Christopher2013-11-141-1/+1
* ARM: produce friendly error for invalid inline asmTim Northover2013-11-141-0/+16
* Add a triple and switch test to FileCheck.Rafael Espindola2013-11-141-1/+8
* Error if we see an alias to a declaration.Rafael Espindola2013-11-149-26/+70
* AVX-512: Handled extractelement from mask vector;Elena Demikhovsky2013-11-142-0/+33
* R600/SI: Add testcase for problem I ran intoMatt Arsenault2013-11-141-0/+18
* Minor extension to llvm.experimental.patchpoint: don't require a call.Andrew Trick2013-11-141-0/+16
* Add test case for AArch64 NEON instruction set misc.Kevin Qin2013-11-141-0/+1609
* Don't mangle \n and "Rafael Espindola2013-11-141-0/+6
* Implement aarch64 neon instruction class SIMD misc.Kevin Qin2013-11-141-112/+56
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-141-0/+828
* Take care of long short branch immediate instructions for mips16 inReed Kotler2013-11-132-0/+59
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-134-20/+27
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-138-109/+128
* [AArch64] Add support for legacy AArch32 NEON scalar shift by immediateChad Rosier2013-11-131-18/+18
* Enable generating legacy IT block for AArch32Weiming Zhao2013-11-139-2/+15
* Remove AllowQuotesInName and friends from MCAsmInfo.Rafael Espindola2013-11-132-14/+14
* XCore target: implement exception handlingRobert Lytton2013-11-132-8/+137
* Allow the code which returns the length for inline assembler to knowReed Kotler2013-11-131-0/+29
* Add a test case to verify that misusing anyregcc crashes as expected.Andrew Trick2013-11-131-0/+17
* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-131-0/+51
* SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.Juergen Ributzka2013-11-131-0/+42
* Cleanup the stackmap operand folding code and fix a corner case.Andrew Trick2013-11-121-1/+21
* [mips] Fix a bug in function CC_MipsO32_FP64. The second double precisionAkira Hatanaka2013-11-121-6/+6
* [mips] Run test case with command line option -mattr=+fp64.Akira Hatanaka2013-11-121-16/+39
* [mips] Fix and re-enable a test case that has been disabled for a long time.Akira Hatanaka2013-11-121-99/+120
* Simplify operand folding when rematerializing a load.Andrew Trick2013-11-121-11/+6
* [mips][msa] Enable inlinse assembly for MSA.Daniel Sanders2013-11-121-0/+34
* [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. n...Daniel Sanders2013-11-122-1/+139
* [ARM] Add support for FP_HP_extension build attributeBradley Smith2013-11-122-6/+24
* [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from norm...Daniel Sanders2013-11-121-0/+248
* [mips][msa] Change constant used in ori tests to avoid conflict with bseti (a...Daniel Sanders2013-11-121-16/+16
* XCore target: fix bug in aligning 'byval i8*' on the stackRobert Lytton2013-11-121-0/+15
* XCore target test for hidden declarationRobert Lytton2013-11-121-1/+5
* Add XCore support for ATOMIC_FENCE.Robert Lytton2013-11-121-0/+16
* XCore target: return error for unsupported alignmentRobert Lytton2013-11-121-0/+9
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-1253-280/+279
* Change the default branch instruction to be the 16 bit variety for mips16.Reed Kotler2013-11-121-0/+37
* R600/SI: Add test that fails due to requiring i64 mul for pointersMatt Arsenault2013-11-111-0/+18
* Fix the recently added anyregcc convention to handle spilled operands.Andrew Trick2013-11-111-8/+37
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-1125-280/+246
* [mips] Partially revert r193641. Stack alignment should not be determined byAkira Hatanaka2013-11-111-2/+1
* [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment ...Justin Holewinski2013-11-111-0/+26
* [NVPTX] Fix logic error in loading vector parameters of more than 4 componentsJustin Holewinski2013-11-111-0/+13
* [AArch64] The shift right/left and insert immediate builtins expect 3Chad Rosier2013-11-111-14/+18
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point i...Chad Rosier2013-11-111-8/+56
* Vector forms of SHL, SRA, and SRL can be constant folded using SimplifyVBinOp...Daniel Sanders2013-11-111-0/+70
* [mips][msa] CHECK-DAG-ize MSA 3r-a.ll test.Matheus Almeida2013-11-111-192/+336
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