| Commit message (Expand) | Author | Age | Files | Lines |
* | The lower invoke pass needs to have unreachable code elimination run after it | Bill Wendling | 2010-08-04 | 1 | -0/+39 |
* | PR7814: Truncates cannot be ignored for signed comparisons. | Eli Friedman | 2010-08-04 | 1 | -0/+36 |
* | Testcase for r110248. | Bill Wendling | 2010-08-04 | 1 | -0/+65 |
* | call-imm.ll test case regex fix. Patch by Dimitry Andric! | Stuart Hastings | 2010-08-04 | 1 | -1/+1 |
* | Make SPU backend handle insertelement and | Kalle Raiskila | 2010-08-04 | 2 | -0/+25 |
* | Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA | Bob Wilson | 2010-08-04 | 1 | -0/+24 |
* | OK, that's it. This test is going away now. But don't worry, I am taking it to a | Jakob Stoklund Olesen | 2010-08-03 | 1 | -361/+0 |
* | More SPU v2f32 stuff added: insertelement and shuffle. | Kalle Raiskila | 2010-08-02 | 1 | -0/+10 |
* | Add preliminary v2f32 support for SPU. Like with v2i32, we just | Kalle Raiskila | 2010-08-02 | 1 | -0/+35 |
* | Add preliminary v2i32 support for SPU backend. As there are no | Kalle Raiskila | 2010-08-02 | 1 | -0/+57 |
* | PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR. | Eli Friedman | 2010-08-02 | 1 | -7/+11 |
* | PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually | Eli Friedman | 2010-08-01 | 1 | -0/+11 |
* | Revert new AVX intrinsic tests. They are breaking buildbots and Bruno is | Bob Wilson | 2010-07-31 | 2 | -2006/+0 |
* | A *bunch* of tests for AVX intrinsics | Bruno Cardoso Lopes | 2010-07-30 | 2 | -0/+2006 |
* | Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctly | Eli Friedman | 2010-07-30 | 1 | -0/+14 |
* | Many Thumb2 instructions can reference the full ARM register set (i.e., | Jim Grosbach | 2010-07-30 | 2 | -7/+26 |
* | Implement vector constants which are splat of | Dale Johannesen | 2010-07-29 | 1 | -0/+38 |
* | Implement a vectorized algorithm for <16 x i8> << <16 x i8> | Nate Begeman | 2010-07-28 | 1 | -1/+12 |
* | ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller ... | Nate Begeman | 2010-07-27 | 1 | -0/+14 |
* | Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECT... | Nate Begeman | 2010-07-27 | 1 | -0/+6 |
* | Currently EH lowering code expects typeinfo to be global only. | Anton Korobeynikov | 2010-07-26 | 1 | -0/+95 |
* | - Allow target to specify when is register pressure "too high". In most cases, | Evan Cheng | 2010-07-23 | 1 | -8/+8 |
* | Use the proper type for shift counts. This fixes a bootstrap error. | Dan Gohman | 2010-07-23 | 1 | -0/+22 |
* | DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits | Dan Gohman | 2010-07-23 | 1 | -0/+18 |
* | Custom lower the memory barrier instructions and add support | Eric Christopher | 2010-07-22 | 2 | -0/+28 |
* | More register pressure aware scheduling work. | Evan Cheng | 2010-07-21 | 1 | -8/+8 |
* | Baby steps towards ARM fast-isel. | Eric Christopher | 2010-07-21 | 1 | -0/+15 |
* | Fix calling convention on ARM if vfp2+ is enabled. | Rafael Espindola | 2010-07-21 | 1 | -5/+23 |
* | Fix SCEV denormalization of expressions where the exit value from | Dan Gohman | 2010-07-20 | 1 | -0/+99 |
* | update tests for smarter BIC usage | Jim Grosbach | 2010-07-20 | 3 | -6/+4 |
* | The same problem was being tracked in PR7652. | Duncan Sands | 2010-07-20 | 1 | -0/+1 |
* | Fix PR7174, a couple o Mips fixes: | Bruno Cardoso Lopes | 2010-07-20 | 1 | -0/+33 |
* | Fix Mips PR7473. Patch by stetorvs@gmail.com | Bruno Cardoso Lopes | 2010-07-20 | 1 | -0/+21 |
* | After a custom inserter, in a block which has constant instructions, | Dan Gohman | 2010-07-19 | 1 | -0/+16 |
* | Remove r108639 now that it is handled by InstCombine instead. | Owen Anderson | 2010-07-19 | 1 | -17/+0 |
* | Add a testcase for r108639. | Owen Anderson | 2010-07-18 | 1 | -0/+17 |
* | Add combiner patterns to more effectively utilize the BFI (bitfield insert) | Jim Grosbach | 2010-07-17 | 2 | -0/+46 |
* | Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction | Jim Grosbach | 2010-07-16 | 2 | -0/+34 |
* | Consider this function: | Bill Wendling | 2010-07-16 | 4 | -16/+27 |
* | Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill | Jakob Stoklund Olesen | 2010-07-16 | 1 | -133/+0 |
* | Feed the right output into FileCheck. | Benjamin Kramer | 2010-07-16 | 1 | -2/+2 |
* | Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. | Jakob Stoklund Olesen | 2010-07-16 | 1 | -1/+1 |
* | Add forgotten test case. | Jakob Stoklund Olesen | 2010-07-16 | 1 | -0/+28 |
* | Use the source-order scheduler instead of the "fast" scheduler at -O0, | Dan Gohman | 2010-07-16 | 2 | -3/+3 |
* | The SelectionDAGBuilder's handling of debug info, on rare | Dale Johannesen | 2010-07-16 | 1 | -0/+147 |
* | Revert. This isn't the correct way to go. | Bill Wendling | 2010-07-15 | 2 | -12/+3 |
* | Handle code gen for the unreachable instruction if it's the only instruction in | Bill Wendling | 2010-07-15 | 2 | -3/+12 |
* | Split -enable-finite-only-fp-math to two options: | Evan Cheng | 2010-07-15 | 4 | -5/+5 |
* | fix the definitions of ConstTextCoalSection/ConstDataCoalSection | Chris Lattner | 2010-07-15 | 1 | -2/+2 |
* | Fix crash reported in PR7653. | Devang Patel | 2010-07-15 | 1 | -0/+12 |