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* Add integer promotion support for vselectNadav Rotem2011-09-141-0/+17
* Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "m...Bruno Cardoso Lopes2011-09-141-0/+14
* Remove ancient debug info constructs from test cases, they are not relevant t...Devang Patel2011-09-142-11/+0
* Remove unnecessary old test.Devang Patel2011-09-141-49/+0
* Delete test cases that generate code for allegrex/psp and cannot be repurposed.Akira Hatanaka2011-09-132-45/+0
* Error out on CodeGen of unaligned load/store. Fix test so it isn't accidenta...Eli Friedman2011-09-131-2/+2
* Add pattern used to match MipsLo, which is needed when the instruction selectorAkira Hatanaka2011-09-131-0/+19
* Disable tests which generate code for allegrex or psp.Akira Hatanaka2011-09-132-16/+22
* update checked patternNadav Rotem2011-09-131-1/+19
* Add vselect target support for targets that do not support blend but do supportNadav Rotem2011-09-131-0/+37
* Generalize this test's CHECK statements to handle different indvars modes.Andrew Trick2011-09-131-2/+2
* Change testcase commandline to be more strict and silence buildbotsBruno Cardoso Lopes2011-09-121-1/+1
* Fix PR10845. SUBREG_TO_REG shouldn't be used when the input andBruno Cardoso Lopes2011-09-121-0/+14
* Revert the wrong part of r139528, and fix testcases.Bruno Cardoso Lopes2011-09-122-4/+4
* Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.Bruno Cardoso Lopes2011-09-122-0/+37
* Fix mistake in test runline.Eli Friedman2011-09-121-1/+1
* Associate a MemOperand with LDWCP nodes introduced during ISel.Richard Osborne2011-09-121-0/+18
* Really un-XFAIL the testcase, like I said I would in r139458.Eli Friedman2011-09-101-1/+0
* Fixed an assert from:Richard Trieu2011-09-101-0/+1
* Fix test cases.Akira Hatanaka2011-09-0915-53/+53
* Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the s...Eli Friedman2011-09-091-0/+23
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-098-80/+10
* Implement vector-select support for avx256. Refactor the vblend implementatio...Nadav Rotem2011-09-091-0/+38
* Drop support for Allegrex. Allegrex implements a variant of Mips2.Akira Hatanaka2011-09-098-16/+33
* Change default target architecture from Mips1 to Mips32r1 in preparation forAkira Hatanaka2011-09-094-6/+6
* Directly point debug info to the stack slot of the arugment, instead of tryin...Devang Patel2011-09-081-0/+65
* Add a AVX version of a simple i64 -> f64 bitcast. This could beBruno Cardoso Lopes2011-09-081-0/+10
* Reapply testcase from r139309!Bruno Cardoso Lopes2011-09-081-0/+47
* Remove this crashing test, until I figure out what's going wrong hereBruno Cardoso Lopes2011-09-081-47/+0
* Add AVX versions of blend vector operations and fix some issues noticedBruno Cardoso Lopes2011-09-082-0/+47
* Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.Bruno Cardoso Lopes2011-09-081-0/+25
* This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.llNadav Rotem2011-09-081-15/+0
* add a testcase for the previous patchNadav Rotem2011-09-081-0/+47
* Add X86-SSE4 codegen support for vector-select.Nadav Rotem2011-09-081-1/+1
* Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly ...Eli Friedman2011-09-071-1/+1
* Another forgotten trampoline testcase.Duncan Sands2011-09-071-0/+16
* Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures...Eli Friedman2011-09-071-1/+1
* While sinking machine instructions, sink matching DBG_VALUEs also otherwise l...Devang Patel2011-09-071-0/+49
* Disable these tests harder. They're XFAIL'd, but that means they still run, andNick Lewycky2011-09-064-4/+8
* Fix fall outs from my recent change on how carry bit is modeled during isel.Evan Cheng2011-09-061-0/+10
* Atomic pseudos don't use (as in read) CPSR. They clobber it.Jakob Stoklund Olesen2011-09-062-4/+4
* Split the init.trampoline intrinsic, which currently combines GCC'sDuncan Sands2011-09-062-4/+8
* Revert r129875, XFAILing this test for arm, since the fix was reverted.Dan Gohman2011-09-031-0/+1
* Pseudo CMOV instructions don't clobber EFLAGS.Jakob Stoklund Olesen2011-09-022-6/+6
* Try to eliminate the use of the 'unwind' instruction.Bill Wendling2011-09-021-1/+1
* Don't fast-isel for atomic load/store; some cases require extra handling miss...Eli Friedman2011-09-022-0/+2
* Better fix for this testcase. Update it to the new EH scheme entirely.Bill Wendling2011-09-021-6/+7
* Update for new EH stuff. (I'm not sure if this is 100% correct.)Bill Wendling2011-09-021-1/+1
* Darwin wants ctors/dtors to be ordered the other way round to linux.Duncan Sands2011-09-021-9/+16
* Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.Kalle Raiskila2011-09-021-1/+12