| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add VSELECT to LegalizeVectorTypes::ScalariseVectorResult. Previously it wou... | Pete Cooper | 2012-04-03 | 1 | -0/+8 |
| * | Add an additional testcase which checks ops with multiple users. | Nadav Rotem | 2012-04-03 | 1 | -0/+12 |
| * | Allocate virtual registers in ascending order. | Jakob Stoklund Olesen | 2012-04-02 | 5 | -15/+36 |
| * | During two-address lowering, rescheduling an instruction does not untie | Lang Hames | 2012-04-02 | 1 | -0/+24 |
| * | No need to run llvm-as. | Rafael Espindola | 2012-04-02 | 1 | -1/+1 |
| * | Optimizing swizzles of complex shuffles may generate additional complex shuff... | Nadav Rotem | 2012-04-02 | 1 | -0/+17 |
| * | Enable prefetch generation on PPC64. | Hal Finkel | 2012-04-01 | 1 | -0/+15 |
| * | This commit contains a few changes that had to go in together. | Nadav Rotem | 2012-04-01 | 6 | -14/+28 |
| * | Add instruction itinerary for the PPC64 A2 core. | Hal Finkel | 2012-04-01 | 1 | -0/+33 |
| * | Add a triple to the test. | Rafael Espindola | 2012-03-31 | 1 | -1/+1 |
| * | Teach CodeGen's version of computeMaskedBits to understand the range metadata. | Rafael Espindola | 2012-03-31 | 1 | -0/+14 |
| * | ARM target should allow codegenprep to duplicate ret instructions to enable t... | Evan Cheng | 2012-03-30 | 1 | -0/+42 |
| * | Testcase for r153710. | Bill Wendling | 2012-03-30 | 1 | -0/+35 |
| * | Add testcase for r153705 | Bill Wendling | 2012-03-30 | 1 | -0/+59 |
| * | Change the constant in this testcase so that it results in a constant pool | Lang Hames | 2012-03-29 | 1 | -3/+3 |
| * | The shuffle scheduler is only available in asserts build - make misched-new.ll | Lang Hames | 2012-03-29 | 1 | -0/+1 |
| * | Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in 6... | Lang Hames | 2012-03-29 | 1 | -2/+3 |
| * | Expand FREM. | Akira Hatanaka | 2012-03-29 | 1 | -0/+13 |
| * | For X86, change load/dec-or-inc/store into dec-or-inc, respectively. | Joel Jones | 2012-03-29 | 2 | -67/+179 |
| * | Reverted to revision 153616 to unblock build | Joel Jones | 2012-03-29 | 2 | -179/+67 |
| * | For X86, change load/dec-or-inc/store into dec-or-inc, respectively. | Joel Jones | 2012-03-29 | 2 | -67/+179 |
| * | Don't kill the base register when expanding strd. | Jakob Stoklund Olesen | 2012-03-28 | 1 | -0/+15 |
| * | Spill DPair registers, not just QPR. | Jakob Stoklund Olesen | 2012-03-28 | 1 | -1/+15 |
| * | Fix test case. | Akira Hatanaka | 2012-03-28 | 1 | -0/+2 |
| * | Add a test for the previous commit. Also, remove two tests that were | Eric Christopher | 2012-03-27 | 1 | -108/+0 |
| * | Post-ra LICM should take care not to hoist an instruction that would clobber a | Evan Cheng | 2012-03-27 | 1 | -0/+59 |
| * | ARM has a peephole optimization which looks for a def / use pair. The def | Evan Cheng | 2012-03-26 | 1 | -0/+33 |
| * | Remove stale CBackend tests. | Benjamin Kramer | 2012-03-26 | 52 | -627/+0 |
| * | Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu | Eli Bendersky | 2012-03-25 | 17 | -136/+17 |
| * | Fix small-integer VAARG on SVR4 ABI PPC64. | Hal Finkel | 2012-03-24 | 1 | -0/+20 |
| * | Remove -enable-lsr-nested in time for 3.1. | Andrew Trick | 2012-03-22 | 5 | -1138/+0 |
| * | [fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271% | Chad Rosier | 2012-03-22 | 1 | -0/+9 |
| * | misched: tag a few XFAILs that I plan to fix | Andrew Trick | 2012-03-21 | 4 | -2/+10 |
| * | I meant to disable this test, not XFAIL it | Andrew Trick | 2012-03-21 | 1 | -2/+2 |
| * | misched: beginning to add unit tests | Andrew Trick | 2012-03-21 | 1 | -0/+20 |
| * | Fix test case from r153135. | Chad Rosier | 2012-03-20 | 1 | -1/+1 |
| * | [avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to | Chad Rosier | 2012-03-20 | 1 | -0/+89 |
| * | [avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove | Chad Rosier | 2012-03-20 | 1 | -1/+0 |
| * | Fix test. | Chad Rosier | 2012-03-20 | 1 | -1/+1 |
| * | [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads. | Chad Rosier | 2012-03-20 | 1 | -0/+13 |
| * | It's possible to have a constant expression who's size is quite big (e.g., | Bill Wendling | 2012-03-20 | 1 | -0/+17 |
| * | Perform mul combine when multiplying wiht negative constants. | Anton Korobeynikov | 2012-03-19 | 1 | -0/+42 |
| * | This patch adds X86 instruction itineraries for non-pseudo opcodes in | Preston Gurd | 2012-03-19 | 1 | -1/+1 |
| * | [fast-isel] Address Eli's comments for r152847. Specifically, add a test case | Chad Rosier | 2012-03-15 | 1 | -0/+19 |
| * | ARM case-insensitive checking for APSR_nzcv. | Jim Grosbach | 2012-03-15 | 3 | -4/+4 |
| * | Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on | Lang Hames | 2012-03-15 | 2 | -27/+3 |
| * | When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add... | Nadav Rotem | 2012-03-15 | 1 | -0/+10 |
| * | [avx] Add patterns for VINSERTF128rm. | Chad Rosier | 2012-03-15 | 1 | -0/+12 |
| * | DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to | Evan Cheng | 2012-03-13 | 1 | -0/+16 |
| * | Fix a regression from r147481. | Chad Rosier | 2012-03-09 | 1 | -0/+12 |
