aboutsummaryrefslogtreecommitdiffstats
path: root/test/CodeGen
Commit message (Collapse)AuthorAgeFilesLines
* Implement multiple with overflow by 2 with an add instruction.Evan Cheng2009-01-271-0/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63090 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a regression test for x86-64 red zone usage.Dan Gohman2009-01-271-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63075 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3393, which amounts to a bug in the expensiveDuncan Sands2009-01-261-0/+16
| | | | | | | | | | checking logic. Rather than make the checking more complicated, I've tweaked some logic to make things conform to how the checking thought things ought to be, since this results in a simpler "mental model". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63048 91177308-0d34-0410-b5e6-96231b3b80d8
* At Nick Lewycky's request, rename this test with a more informative name.Dan Gohman2009-01-261-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63042 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside ↵Evan Cheng2009-01-261-0/+45
| | | | | | callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63022 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-265-69/+84
| | | | | | | | | | | | | | | | | - Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
* Map address space 256 to gs; similar mappings could be supported for theNate Begeman2009-01-261-0/+8
| | | | | | | | other x86 segments. address space 0 is stack/default, 1-255 are reserved for client use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62980 91177308-0d34-0410-b5e6-96231b3b80d8
* revert this patch for now, because Codegen does still want to generate SSE code,Torok Edwin2009-01-251-0/+2
| | | | | | | for example in the case of va-args. XFAIL associated tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62972 91177308-0d34-0410-b5e6-96231b3b80d8
* If user explicitly asks not to use SSE, don't force it. This fixes LLVM part ↵Torok Edwin2009-01-251-0/+20
| | | | | | of PR3402. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62967 91177308-0d34-0410-b5e6-96231b3b80d8
* Private linkage support for PPC / Darwin.Evan Cheng2009-01-251-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62955 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach 2addr pass to be do more commuting. If both uses of a two-address ↵Evan Cheng2009-01-254-3/+28
| | | | | | | | | | | | | | | | | | | | | | instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue. %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 %reg1029<def> = MOV8rr %reg1028 %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> insert => %reg1030<def> = MOV8rr %reg1028 %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead> In this case, it might not be possible to coalesce the second MOV8rr instruction if the first one is coalesced. So it would be profitable to commute it: %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1 %reg1029<def> = MOV8rr %reg1028 %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead> insert => %reg1030<def> = MOV8rr %reg1029 %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62954 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a PR comment to this test.Dan Gohman2009-01-241-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62921 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test to reflect command line option name change.Evan Cheng2009-01-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62836 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't create ISD::FNEG nodes after legalize if they aren't legal.Dan Gohman2009-01-221-0/+1145
| | | | | | | | | | | | | | | Simplify x+0 to x in unsafe-fp-math mode. This avoids a bunch of redundant work in many cases, because in unsafe-fp-math mode, ISD::FADD with a constant is considered free to negate, so the DAGCombiner often negates x+0 to -0-x thinking it's free, when in reality the end result is -x, which is more expensive than x. Also, combine x*0 to 0. This fixes PR3374. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62789 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not use buggy llvm-gcc to generate testcases.Devang Patel2009-01-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62770 91177308-0d34-0410-b5e6-96231b3b80d8
* Now with RUN line.Bill Wendling2009-01-211-2/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62716 91177308-0d34-0410-b5e6-96231b3b80d8
* Run this through -simplifycfg and -mem2reg to test only what we need to test.Bill Wendling2009-01-211-90/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62714 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify ReduceLoadWidth's logic: it doesn't need several differentDan Gohman2009-01-211-0/+46
| | | | | | | | | special cases after producing the new reduced-width load, because the new load already has the needed adjustments built into it. This fixes several bugs due to the special cases, including PR3317. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62692 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a recent regression. ClrOpcode is not set for i8; for i8, ifDan Gohman2009-01-211-0/+21
| | | | | | | | we want to clear %ah to zero before a division, just use a zero-extending mov to %al. This fixes PR3366. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62691 91177308-0d34-0410-b5e6-96231b3b80d8
* Let's try to have our cake and eat it to: moveDuncan Sands2009-01-211-282/+0
| | | | | | | | | this test into FrontendC to ensure that llvm-gcc is available; assemble using "llvm-gcc -xassembler" rather than "as". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62683 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't rely on grep -w working.Duncan Sands2009-01-211-16/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62682 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-211-3/+3
| | | | | | | | | | | | | | - Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
* Favors generating "not" over "xor -1". For example.Evan Cheng2009-01-211-1/+1
| | | | | | | | | | | | | | | | | | unsigned test(unsigned a) { return ~a; } llvm used to generate: movl $4294967295, %eax xorl 4(%esp), %eax Now it generates: movl 4(%esp), %eax notl %eax It's 3 bytes shorter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62661 91177308-0d34-0410-b5e6-96231b3b80d8
* Be more aggressive about renumbering vregs after splitting them.Owen Anderson2009-01-211-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62639 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't bother running the assembler, we don't know that it will be configuredChris Lattner2009-01-201-1/+1
| | | | | | | for whatever llc defaults to. This fixes PR3363 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62619 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR3243: a LiveVariables bug. When HandlePhysRegKill is checking whether ↵Evan Cheng2009-01-201-0/+15
| | | | | | the last reference is also the last def (i.e. dead def), it should also check if last reference is the current machine instruction being processed. This can happen when it is processing a physical register use and setting the current machine instruction as sub-register's last ref. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62617 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test case for PR3154.Evan Cheng2009-01-201-0/+104
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62604 91177308-0d34-0410-b5e6-96231b3b80d8
* Testcase for limited precision stuff.Bill Wendling2009-01-201-0/+133
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62572 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a dagcombine to not generate loads of non-round integer types,Dan Gohman2009-01-201-0/+14
| | | | | | | | as its comment says, even in the case where it will be generating extending loads. This fixes PR3216. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62557 91177308-0d34-0410-b5e6-96231b3b80d8
* Make linear scan's trivial coalescer slightly more aggressive.Evan Cheng2009-01-201-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62547 91177308-0d34-0410-b5e6-96231b3b80d8
* Move & restructure test per review.Dale Johannesen2009-01-191-77/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62538 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SelectionDAG::ReplaceAllUsesWith to behave correctly whenDan Gohman2009-01-191-0/+8
| | | | | | | | | | | | | | uses are added to the From node while it is processing From's use list, because of automatic local CSE. The fix is to avoid visiting any new uses. Fix a few places in the DAGCombiner that assumed that after a RAUW call, the From node has no users and may be deleted. This fixes PR3018. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62533 91177308-0d34-0410-b5e6-96231b3b80d8
* compile-time fmod was done incorrectly. PR 3316.Dale Johannesen2009-01-191-0/+77
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62528 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify Intrinsic::dbg_declare. Devang Patel2009-01-191-9/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62526 91177308-0d34-0410-b5e6-96231b3b80d8
* DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX ↵Evan Cheng2009-01-191-0/+7
| | | | | | instead of sign extending the low part (in AX/EAX/RAX) into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62519 91177308-0d34-0410-b5e6-96231b3b80d8
* Now not UINT_TO_FP is legal (it's marked custom), dag combiner won'tEvan Cheng2009-01-191-0/+1
| | | | | | | optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62504 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix rdar://6505632, an llc crash on 483.xalancbmkChris Lattner2009-01-181-0/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62470 91177308-0d34-0410-b5e6-96231b3b80d8
* Testcase for last commit.Bill Wendling2009-01-171-0/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62418 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix MatchAddress bug that's preventing negative displacement from being ↵Evan Cheng2009-01-172-1/+19
| | | | | | folded in 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62413 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify extract element of a scalar to vector.Mon P Wang2009-01-171-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62383 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PPC ISD::Declare isel and eliminate the need for ↵Evan Cheng2009-01-161-0/+19
| | | | | | PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62373 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the post-RA scheduler on this test, since it uses aDan Gohman2009-01-161-1/+2
| | | | | | | | simple %prcontext which doesn't find what it's looking for if the scheduler has rearranged the instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62363 91177308-0d34-0410-b5e6-96231b3b80d8
* CreateVirtualRegisters does trivial copy coalescing. If a node def is used ↵Evan Cheng2009-01-161-0/+50
| | | | | | by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62356 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for non-zero __builtin_return_address values on X86.Bill Wendling2009-01-161-0/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62338 91177308-0d34-0410-b5e6-96231b3b80d8
* Added missing support to widen an operand from a bit convert.Mon P Wang2009-01-151-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62285 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Alpha test and support for private linkage.Rafael Espindola2009-01-151-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62282 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand insert/extract of a <4 x i32> with a variable index.Mon P Wang2009-01-151-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62281 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the private linkage.Rafael Espindola2009-01-159-0/+190
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't fold address calculations which use negative offsets intoRichard Osborne2009-01-151-0/+12
| | | | | | | the ADDRspii addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62258 91177308-0d34-0410-b5e6-96231b3b80d8
* - Convert remaining i64 custom lowering into custom instruction emissionScott Michel2009-01-152-9/+40
| | | | | | | | | | | | | | sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom DAG node types as needed. - i64 mul is now a legal instruction, but emits an instruction sequence that stretches tblgen and the imagination, as well as violating laws of several small countries and most southern US states (just kidding, but looking at a function with 80+ parameters is really weird and just plain wrong.) - Update tests as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62254 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-02-05 03:54:33 +0000