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* [fast-isel] Tell fast-isel to do nothing with the new donothing intrinsic.Chad Rosier2012-07-061-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159837 91177308-0d34-0410-b5e6-96231b3b80d8
* Attempt to fix windows buildbots. Patch by James Benton.Duncan Sands2012-07-061-5/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159826 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/sext-setcc-self.ll: Mark it as XFAIL: cygwin,mingw32,win32. ↵NAKAMURA Takumi2012-07-061-0/+4
| | | | | | Investigating. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159820 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r159804, "[arm-fast-isel] Add support for vararg function calls."NAKAMURA Takumi2012-07-061-43/+0
| | | | | | It broke LLVM :: CodeGen/Thumb2/large-call.ll on several hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159817 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm-fast-isel] Add support for vararg function calls.Jush Lu2012-07-061-0/+43
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159804 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific inline asm operand modifier D.Jack Carter2012-07-051-22/+53
| | | | | | | | | | | | | Print the second half of a double word operand. The include list was cleaned up a bit as well. Also the test case was modified to test for both big and little patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159787 91177308-0d34-0410-b5e6-96231b3b80d8
* test case for r159770.Akira Hatanaka2012-07-051-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159771 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1Duncan Sands2012-07-051-0/+55
| | | | | | | booleans. Patch by James Benton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159739 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure CopyToReg nodes are always glued to the call instruction.Jakob Stoklund Olesen2012-07-042-5/+21
| | | | | | | | | | | | | The CopyToReg nodes that set up the argument registers before a call must be glued to the call instruction. Otherwise, the scheduler may emit the physreg copies long before the call, causing long live ranges for the fixed registers. Besides disabling good register allocation, that can also expose problems when EmitInstrWithCustomInserter() splits a basic block during the live range of a physreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159721 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a testcase for pr13209. It is not a great test, but it still fails ifRafael Espindola2012-07-041-0/+74
| | | | | | | 159509 and 159479 are reverted. It would be really nice to be able to run just the coalescer :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159715 91177308-0d34-0410-b5e6-96231b3b80d8
* Add early if-conversion support to X86.Jakob Stoklund Olesen2012-07-041-0/+39
| | | | | | | | | Implement the TII hooks needed by EarlyIfConversion to create cmov instructions and estimate their latency. Early if-conversion is still not enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159695 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/SPARC/private.ll: Fixup. Forgot to prune old RUN lines.NAKAMURA Takumi2012-07-031-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159643 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/SPARC/private.ll: FileCheck-ize.NAKAMURA Takumi2012-07-031-1/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159642 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/sincos.ll: FileCheck-ize.NAKAMURA Takumi2012-07-031-4/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159639 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/fabs.ll: FileCheck-ize.NAKAMURA Takumi2012-07-031-5/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159638 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/2007-09-05-InvalidAsm.ll: FileCheck-ize.NAKAMURA Takumi2012-07-031-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159637 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/X86/2004-03-30-Select-Max.ll: FileCheck-ize.NAKAMURA Takumi2012-07-031-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159636 91177308-0d34-0410-b5e6-96231b3b80d8
* mips32 long long register inline asm constraint support.Jack Carter2012-07-021-0/+6
| | | | | | | | inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159625 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert " mips32 long long register inline asm constraint support." asEric Christopher2012-07-021-6/+0
| | | | | | | | it appears to be breaking the bots. This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159619 91177308-0d34-0410-b5e6-96231b3b80d8
* deleted test/CodeGen/Mips/inlineasm-cnstrnt-bad-r-1.llJack Carter2012-07-021-17/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159617 91177308-0d34-0410-b5e6-96231b3b80d8
* mips32 long long register inline asm constraint support.Jack Carter2012-07-021-0/+6
| | | | | | | | inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed. This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159610 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend TargetPassConfig to allow running only a subset of the normal passes.Bob Wilson2012-07-021-0/+10
| | | | | | | | | | | | | | | | | This is still a work in progress but I believe it is currently good enough to fix PR13122 "Need unit test driver for codegen IR passes". For example, you can run llc with -stop-after=loop-reduce to have it dump out the IR after running LSR. Serializing machine-level IR is not yet supported but we have some patches in progress for that. The plan is to serialize the IR to a YAML file, containing separate sections for the LLVM IR, machine-level IR, and whatever other info is needed. Chad suggested that we stash the stop-after pass in the YAML file and use that instead of the start-after option to figure out where to restart the compilation. I think that's a great idea, but since it's not implemented yet I put the -start-after option into this patch for testing purposes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159570 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the remaining TCL-style quotes found in the testsuite. This isChandler Carruth2012-07-0238-46/+46
| | | | | | | | | | | | | | | | | another mechanical change accomplished though the power of terrible Perl scripts. I have manually switched some "s to 's to make escaping simpler. While I started this to fix tests that aren't run in all configurations, the massive number of tests is due to a really frustrating fragility of our testing infrastructure: things like 'grep -v', 'not grep', and 'expected failures' can mask broken tests all too easily. Essentially, I'm deeply disturbed that I can change the testsuite so radically without causing any change in results for most platforms. =/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159547 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert the uses of '|&' to use '2>&1 |' instead, which works on oldChandler Carruth2012-07-0234-37/+37
| | | | | | | | | | versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159544 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not attempt to use ROR for Thumb1.Bob Wilson2012-07-021-2/+4
| | | | | | Patch by Matt Fischer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159538 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the TCL-style quoting in one random test that somehow slippedChandler Carruth2012-07-021-1/+1
| | | | | | | | | through my perl nets. With this, the test suite passes even if I force it to run with the built-in shell test logic, except for a test which REQUIREs shell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159529 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert all tests using TCL-style quoting to use shell-style quoting.Chandler Carruth2012-07-02112-213/+213
| | | | | | | | | | | | | | | | | | | | | | | | This was done through the aid of a terrible Perl creation. I will not paste any of the horrors here. Suffice to say, it require multiple staged rounds of replacements, state carried between, and a few nested-construct-parsing hacks that I'm not proud of. It happens, by luck, to be able to deal with all the TCL-quoting patterns in evidence in the LLVM test suite. If anyone is maintaining large out-of-tree test trees, feel free to poke me and I'll send you the steps I used to convert things, as well as answer any painful questions etc. IRC works best for this type of thing I find. Once converted, switch the LLVM lit config to use ShTests the same as Clang. In addition to being able to delete large amounts of Python code from 'lit', this will also simplify the entire test suite and some of lit's architecture. Finally, the test suite runs 33% faster on Linux now. ;] For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159525 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite three tests that had truly egregious abuses of 'grep' in them toChandler Carruth2012-07-023-32/+643
| | | | | | | | | | | | | | use FileCheck. Aside from removing a dependence on TCL-style quoting, this also makes the tests ... significantly more robust. =] It would be really, *really* great of the maintainer(s) of the CellSPU backend went through and systematically rewrite these tests to use FileCheck. There are a lot more that have nearly this bad of abuses. Another step along the path to a TclTest-free testsuite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159523 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that RegistersDefinedFromSameValue handles one instruction being anRafael Espindola2012-07-011-0/+27
| | | | | | | | | implicit_def, the other instruction can be anything, including instructions that define multiple values. Be careful about that and don't assume what operand 0 is. Fixes pr13249. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159509 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimization of shuffle node that can fit to the register form of VBROADCAST ↵Elena Demikhovsky2012-07-011-0/+96
| | | | | | instruction on AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159504 91177308-0d34-0410-b5e6-96231b3b80d8
* Clear kill flags in InstrEmitter::EmitSubregNode().Jakob Stoklund Olesen2012-06-291-2/+37
| | | | | | | When a local virtual register is made global, make sure to clear any existing kill flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159461 91177308-0d34-0410-b5e6-96231b3b80d8
* In the initial exec mode we always do a load to find the address of a variable.Rafael Espindola2012-06-291-5/+6
| | | | | | | | | Before this patch in pic 32 bit code we would add the global base register and not load from that address. This is a really old bug, but before the introduction of the tls attributes we would never select initial exec for pic code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159409 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: add more GATHER intrinsics in LLVMManman Ren2012-06-291-10/+90
| | | | | | | | | | | | | | | | Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
* add a new @llvm.donothing intrinsic that, well, does nothing, and teach ↵Nuno Lopes2012-06-281-0/+31
| | | | | | CodeGen to ignore calls to it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159383 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips specific inline asm operand modifier 'z' has theJack Carter2012-06-281-0/+12
| | | | | | | | | following description in the gnu sources: Print $0 if operand is zero otherwise print the op normally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159324 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r159240.Akira Hatanaka2012-06-271-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159242 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix llc's -print-before=pass and -print-after=pass.Rafael Espindola2012-06-261-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159227 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-0/+80
| | | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
* There are a number of generic inline asm operand modifiers thatJack Carter2012-06-261-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159203 91177308-0d34-0410-b5e6-96231b3b80d8
* Shuffle optimization for AVX/AVX2.Elena Demikhovsky2012-06-261-0/+21
| | | | | | | | | | | | | | | | | | | | The current patch optimizes frequently used shuffle patterns and gives these instruction sequence reduction. Before: vshufps $-35, %xmm1, %xmm0, %xmm2 ## xmm2 = xmm0[1,3],xmm1[1,3] vpermilps $-40, %xmm2, %xmm2 ## xmm2 = xmm2[0,2,1,3] vextractf128 $1, %ymm1, %xmm1 vextractf128 $1, %ymm0, %xmm0 vshufps $-35, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm0[1,3],xmm1[1,3] vpermilps $-40, %xmm0, %xmm0 ## xmm0 = xmm0[0,2,1,3] vinsertf128 $1, %xmm0, %ymm2, %ymm0 After: vshufps $13, %ymm0, %ymm1, %ymm1 ## ymm1 = ymm1[1,3],ymm0[0,0],ymm1[5,7],ymm0[4,4] vshufps $13, %ymm0, %ymm0, %ymm0 ## ymm0 = ymm0[1,3,0,0,5,7,4,4] vunpcklps %ymm1, %ymm0, %ymm0 ## ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159188 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable the new LoopInfo algorithm by default.Andrew Trick2012-06-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The primary advantage is that loop optimizations will be applied in a stable order. This helps debugging and unit test creation. It is also a better overall implementation without pathologically bad performance on deep functions. On large functions (llvm-stress --size=200000 | opt -loops) Before: 0.1263s After: 0.0225s On deep functions (after tweaking llvm-stress, thanks Nadav): Before: 0.2281s After: 0.0227s See r158790 for more comments. The loop tree is now consistently generated in forward order, but loop passes are applied in reverse order over the program. If we have a loop optimization that prefers forward order, that can easily be achieved by adding a different type of LoopPassManager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159183 91177308-0d34-0410-b5e6-96231b3b80d8
* Make some ugly hacks for inline asm operands which name a specific register ↵Eli Friedman2012-06-251-3/+16
| | | | | | a bit more thorough. PR13196. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159176 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: update peephole optimization.Manman Ren2012-06-251-0/+12
| | | | | | | | | | | | More condition codes are included when deciding whether to remove cmp after a sub instruction. Specifically, we extend from GE|LT|GT|LE to GE|LT|GT|LE|HS|LS|HI|LO|EQ|NE. If we have "sub a, b; cmp b, a; movhs", we should be able to replace with "sub a, b; movls". rdar: 11725965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159166 91177308-0d34-0410-b5e6-96231b3b80d8
* Enforce stricter liveness rules for PHIs.Jakob Stoklund Olesen2012-06-251-0/+26
| | | | | | | | | | | | | Verify that all paths from the entry block to a virtual register read pass through a def. Enable this check even when MRI->isSSA() is false. Verify that the live range of a virtual register is live out of all predecessor blocks, even for PHI-values. This requires that PHIElimination sometimes inserts IMPLICIT_DEF instruction in predecessor blocks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159150 91177308-0d34-0410-b5e6-96231b3b80d8
* Run ProcessImplicitDefs on SSA form where it can be much simpler.Jakob Stoklund Olesen2012-06-251-2/+2
| | | | | | | | | | | Implicitly defined virtual registers can simply have the <undef> bit set on all uses, and copies can be turned into implicit defs recursively. Physical registers are a bit trickier. We handle the common case where a physreg def is used by a nearby instruction in the same basic block. For more complicated cases, just leave the IMPLICIT_DEF instruction in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159149 91177308-0d34-0410-b5e6-96231b3b80d8
* %RCX is not a function live-out in eh.return functions.Jakob Stoklund Olesen2012-06-241-0/+252
| | | | | | | | | | The function live-out registers must be live at all function returns, and %RCX is only used by eh.return. When a function also has a normal return, only %RAX holds a return value. This fixes PR13188. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159116 91177308-0d34-0410-b5e6-96231b3b80d8
* DAG legalisation can now handle illegal fma vector types by scalarisationPete Cooper2012-06-241-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159092 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend the IL for selecting TLS models (PR9788)Hans Wennborg2012-06-233-0/+396
| | | | | | | | | | | | | | | This allows the user/front-end to specify a model that is better than what LLVM would choose by default. For example, a variable might be declared as @x = thread_local(initialexec) global i32 42 if it will not be used in a shared library that is dlopen'ed. If the specified model isn't supported by the target, or if LLVM can make a better choice, a different model may be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159077 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle aliases to tls variables in all architectures, not just x86.Rafael Espindola2012-06-231-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159058 91177308-0d34-0410-b5e6-96231b3b80d8
* (sub X, imm) gets canonicalized to (add X, -imm)Evan Cheng2012-06-231-0/+12
| | | | | | | | | | | | | | | | There are patterns to handle immediates when they fit in the immediate field. e.g. %sub = add i32 %x, -123 => sub r0, r0, #123 Add patterns to catch immediates that do not fit but should be materialized with a single movw instruction rather than movw + movt pair. e.g. %sub = add i32 %x, -65535 => movw r1, #65535 sub r0, r0, r1 rdar://11726136 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159057 91177308-0d34-0410-b5e6-96231b3b80d8
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