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* Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton2012-04-271-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720 91177308-0d34-0410-b5e6-96231b3b80d8
* Specify cpu to unbreak tests.Evan Cheng2012-04-265-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach2012-04-241-9/+9
| | | | | | | | | | | When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add testcases for two-operand variants of VSRA/VRSRA/VSRI.Jim Grosbach2012-04-232-0/+209
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155391 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM mode tests for the NEON vector shift-accumulate tests.Jim Grosbach2012-04-231-0/+105
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155390 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Reformat for ease of reading.Jim Grosbach2012-04-231-95/+102
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155389 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Update NEON assembly two-operand aliases.Jim Grosbach2012-04-202-0/+21
| | | | | | | | Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases for NEON instructions. There's still more to go, but this is a good chunk of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155210 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM some VFP tblgen'erated two-operand aliases.Jim Grosbach2012-04-201-2/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Formatting.Jim Grosbach2012-04-201-53/+45
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155177 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM two-operand forms for vhadd and vhsub instructions.Jim Grosbach2012-04-162-0/+53
| | | | | | rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly two-operand forms for VRSHL.Jim Grosbach2012-04-161-0/+35
| | | | | | rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154840 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Test formatting.Jim Grosbach2012-04-161-53/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154839 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM two-operand aliases for VRHADD instructions.Jim Grosbach2012-04-161-0/+27
| | | | | | rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154832 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Testcase formatting.Jim Grosbach2012-04-161-13/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154831 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VUZP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11222366 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154511 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VZIP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11221911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154505 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-111-1/+1
| | | | | | | | | | | | predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM add missing Thumb1 two-operand aliases for shift-by-immediate.Jim Grosbach2012-04-111-0/+18
| | | | | | rdar://11222742 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154457 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-111-0/+50
| | | | | | | | | | | 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM fix cc_out operand handling for t2SUBrr instructions.Jim Grosbach2012-04-101-0/+12
| | | | | | | | | | | | We were incorrectly conflating some add variants which don't have a cc_out operand with the mirroring sub encodings, which do. Part of the awesome non-orthogonality legacy of thumb1. Similarly, handling of add/sub of an immediate was sometimes incorrectly removing the cc_out operand for add/sub register variants. rdar://11216577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly aliases for add negative immediates using sub.Jim Grosbach2012-04-051-0/+4
| | | | | | | | | | 'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out. Thumb1 aliases for adding a negative immediate to the stack pointer, also. rdar://11192734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154123 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly aliases for two-operand V[R]SHR instructions.Jim Grosbach2012-04-051-0/+70
| | | | | | rdar://11189467 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for 'msr' plain 'cpsr' operand.Jim Grosbach2012-04-051-0/+2
| | | | | | | | Plain 'cpsr' is an alias for 'cpsr_fc'. rdar://11153753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach2012-03-301-2/+5
| | | | | | | | When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg, we want to use the non-negated form to make sure we prefer the normal encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM encoding for VSWP got the second operand incorrect.Jim Grosbach2012-03-301-0/+7
| | | | | | | | | Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach2012-03-301-0/+8
| | | | | | | | | For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2 can be used for this syntax. Prefer the narrow encoding when possible. rdar://11156277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing needs to be paranoid about negative immediates.Jim Grosbach2012-03-301-1/+4
| | | | | | | | Make sure to treat immediates as unsigned when doing relative comparisons. rdar://11153621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy2012-03-303-2/+28
| | | | | | | | | | fixup_arm_condbranch. Patch by Tim Northover! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly 'cmp lr, #0' should not encode using 'cmn'.Jim Grosbach2012-03-291-0/+2
| | | | | | | | | The CMP->CMN alias was matching for an immediate of zero when it should only match for negative values. rdar://11129224 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.Richard Barton2012-03-281-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153573 91177308-0d34-0410-b5e6-96231b3b80d8
* Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnuEli Bendersky2012-03-251-8/+1
| | | | | | | | | | | | | | | | | | * Removed test/lib/llvm.exp - it is no longer needed * Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files left in the test suite so this code is no longer required. test/lit.cfg is now much shorter and clearer * Removed a lot of duplicate code in lit.local.cfg files that need access to the root configuration, by adding a "root" attribute to the TestingConfig object. This attribute is dynamically computed to provide the same information as was previously provided by the custom getRoot functions. * Documented the config.root attribute in docs/CommandGuide/lit.pod git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembling ARM vst2 instructions with double-spaced registers.Kevin Enderby2012-03-202-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM ldm/stm register lists can be out of order.Jim Grosbach2012-03-161-1/+1
| | | | | | | | | | It's not a good style idea, as the registers will be laid down in memory in numerical order, not the order they're in the list, but it's legal. vldm/vstm are stricter. rdar://11064740 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM optional operand on MRC/MCR assembly instructions.Jim Grosbach2012-03-161-0/+8
| | | | | | rdar://11058464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM vmrs system registers mvfr0 and mvfr1 handling.Jim Grosbach2012-03-161-3/+12
| | | | | | rdar://11058464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM case-insensitive checking for APSR_nzcv.Jim Grosbach2012-03-151-2/+4
| | | | | | rdar://11056591 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix VCVT decoding (between floating-point and fixed-point, Floating-point). ↵Kristof Beyls2012-03-151-1/+26
| | | | | | Patch by Richard Barton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM vpush/vpop assembler mnemonics accept an optional size suffix.Jim Grosbach2012-03-051-0/+15
| | | | | | rdar://10988114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM BL/BLX instruction fixups should use relocations.Jim Grosbach2012-02-272-3/+3
| | | | | | | | | | | | | We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace all instances of dg.exp file with lit.local.cfg, since all tests are ↵Eli Bendersky2012-02-162-5/+13
| | | | | | | | | | | run with LIT now and now Dejagnu. dg.exp is no longer needed. Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM ↵James Molloy2012-01-281-0/+6
| | | | | | | | | | and MIPS ELF backends. Fixes PR11877 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy2012-01-261-0/+12
| | | | | | | | | | relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assemly parsing and validation of IT instruction.Jim Grosbach2012-01-251-0/+11
| | | | | | | | | | "Although a Thumb2 instruction, the IT mnemonic shall be permitted in ARM mode, and the condition verified to match the condition code(s) on the following instruction(s)." PR11853 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-251-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VST4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-241-11/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD4(one lane) assembly parsing and encoding.Jim Grosbach2012-01-241-11/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON Two-operand assembly aliases for VSRA.Jim Grosbach2012-01-241-33/+71
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148821 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove redundant test file.Jim Grosbach2012-01-241-98/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148820 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON Two-operand assembly aliases for VSLI.Jim Grosbach2012-01-241-16/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148819 91177308-0d34-0410-b5e6-96231b3b80d8
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