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| author | Jim Grosbach <grosbach@apple.com> | 2012-03-30 18:53:01 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-03-30 18:53:01 +0000 |
| commit | a45e3747e612c00ca4933087d883db77f4547571 (patch) | |
| tree | ae355131579aa49623670813430f6bfe8d45dfa7 /test/MC/ARM | |
| parent | 8f1148bd07d57a1324ed39250642119baa540b7c (diff) | |
| download | external_llvm-a45e3747e612c00ca4933087d883db77f4547571.zip external_llvm-a45e3747e612c00ca4933087d883db77f4547571.tar.gz external_llvm-a45e3747e612c00ca4933087d883db77f4547571.tar.bz2 | |
ARM encoding for VSWP got the second operand incorrect.
Make the non-tied register operand names line up with what the base
class encoding handler expects.
rdar://11157236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM')
| -rw-r--r-- | test/MC/ARM/neon-vswp.s | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/test/MC/ARM/neon-vswp.s b/test/MC/ARM/neon-vswp.s new file mode 100644 index 0000000..2138eed --- /dev/null +++ b/test/MC/ARM/neon-vswp.s @@ -0,0 +1,7 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s + +vswp d1, d2 +vswp q1, q2 + +@ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3] +@ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3] |