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* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-054-0/+90
| | | | | | | | | | | | | | | | | | | These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8]Joey Gouly2013-08-282-0/+30
| | | | | | | | | | | | Fix a few things in one swoop. # Add some negative tests. # Fix some formatting issues. # Add some missing IsThumb / ARMv8 # Fix some outs / ins mistakes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189490 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-272-0/+66
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189388 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add some negative tests for the recent VFP/NEON instructions.Joey Gouly2013-08-272-3/+108
| | | | | | | Fix two issues I found while writing these tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189341 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM vcvt encoding when the number of fractional bits is zero.Mihai Popa2013-08-221-0/+16
| | | | | | | | | | | | | The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189009 91177308-0d34-0410-b5e6-96231b3b80d8
* Make "mov" work for all Thumb2 MOV encodingsMihai Popa2013-08-211-1/+16
| | | | | | | | According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings. To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188901 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 add immediate alias for SPMihai Popa2013-08-191-0/+2
| | | | | | | | | | The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction. All the patch does is adjust a register constraint on an instruction alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188676 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for Thumb2 literal loads with negative zero offsetMihai Popa2013-08-161-0/+12
| | | | | | | | | | Thumb2 literal loads use an offset encoding which allows for negative zero. This fixes parsing and encoding so that #-0 is correctly processed. The parser represents #-0 as INT32_MIN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188549 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Thumb2 aliasing complementary instructions taking modified immediatesMihai Popa2013-08-161-1/+8
| | | | | | | | | | | | | | | | | | | | | | | There are many Thumb instructions which take 12-bit immediates encoded in a special 8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal to transform an assembly instruction to be able to encode the immediate. For example: AND and BIC are complementary instructions; one can switch the AND to a BIC as long as the immediate is complemented. The intent is to switch one instruction into its complementary one when the immediate cannot be encoded in the form requested in the original assembly and when the complementary immediate is encodable. The patch addresses two issues: 1. definition of t2SOImmNot immediate - it has to check that the orignal value is not encoded naturally 2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand rather than the ARM one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188548 91177308-0d34-0410-b5e6-96231b3b80d8
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-162-4/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188513 91177308-0d34-0410-b5e6-96231b3b80d8
* This fixes three issues related to Thumb literal loads:Mihai Popa2013-08-152-6/+21
| | | | | | | | | | 1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020] 2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed 3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen and the ASM parser, so this alias rule really does nothing git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188466 91177308-0d34-0410-b5e6-96231b3b80d8
* ARMv8: SWP and SWPB are obsoleted on ARMv8.Joey Gouly2013-08-131-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188288 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix signed overflow in when computing encodings for ADR instructionsMihai Popa2013-08-131-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188268 91177308-0d34-0410-b5e6-96231b3b80d8
* This fixes the Thumb2 CPS assembly syntax.Mihai Popa2013-08-092-0/+35
| | | | | | | | | | | | | | | In Thumb1, only one variant is supported: CPS{effect} {flags} Thumb2 supports three: CPS{effect}.W {flags} CPS{effect} {flags} {mode} CPS {mode} Canonically, .W should be used only when ambiguity is present between encodings of different width. The wide suffix is still accepted for the latter two forms via aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188071 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembling of Thumb2 branch instructions.Mihai Popa2013-08-096-6/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The long encoding for Thumb2 unconditional branches is broken. Additionally, there is no range checking for target operands; as such for instructions originating in assembly code, only short Thumb encodings are generated, regardless of the bitsize needed for the offset. Adding range checking is non trivial due to the representation of Thumb branch instructions. There is no true difference between conditional and unconditional branches in terms of operands and syntax - even unconditional branches have a predicate which is expected to match that of the IT block they are in. Yet, the encodings and the permitted size of the offset differ. Due to this, for any mnemonic there are really 4 encodings to choose for. The problem cannot be handled in the parser alone or by manipulating td files. Because the parser builds first a set of match candidates and then checks them one by one, whatever tablegen-only solution might be found will ultimately be dependent of the parser's evaluation order. What's worse is that due to the fact that all branches have the same syntax and the same kinds of operands, that order is governed by the lexicographical ordering of the names of operand classes... To circumvent all this, any necessary disambiguation is added to the instruction validation pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
* This corrects creation of operands for t2PLDW. It also removes the ↵Mihai Popa2013-08-062-2/+7
| | | | | | | | | definition of t2PLDWpci, as pldw does not have a literal variant (i.e. pc relative version) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8
* Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc ↵Mihai Popa2013-08-062-15/+14
| | | | | | instead of apsr_nzcv) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187803 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.Joey Gouly2013-08-021-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187666 91177308-0d34-0410-b5e6-96231b3b80d8
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-311-0/+4
| | | | | | | | | | | | While the .td entry is nice and all, it takes a pretty gross hack in ARMAsmParser::ParseInstruction() because of handling of other "subs" instructions to get it to match. Ran it by Jim Grosbach and he said it was about what he expected to make this work given the existing code. rdar://14214063 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530 91177308-0d34-0410-b5e6-96231b3b80d8
* This adds range checking for "ldr Rn, [pc, #imm]" Thumb Mihai Popa2013-07-221-2/+19
| | | | | | | | | | instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186831 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.Joey Gouly2013-07-192-0/+74
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186688 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.Tilmann Scheller2013-07-192-0/+10
| | | | | | | | | | See A8.8.127 in ARM DDI 0406C.b. Related to <rdar://problem/14403733>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186682 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add NEON instructions VCVT{A, N, P, M}.Joey Gouly2013-07-182-0/+72
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186574 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Thumb tests for the ARMv8 FP instructions that I recently added.Joey Gouly2013-07-181-0/+130
| | | | | | | Also, fix the namespace for two instructions that I missed previously. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186572 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the tests that I forgot to 'svn add' with my previous commit (r186504).Joey Gouly2013-07-172-0/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186506 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add support for the Thumb2 PLI alternate literal form.Tilmann Scheller2013-07-161-0/+4
| | | | | | | | | | | | This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>] See A8.8.129 in the ARM ARM (DDI 0406C.b). Fixes <rdar://problem/14403733>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186459 91177308-0d34-0410-b5e6-96231b3b80d8
* Add newlines at end of test files, no functionality changeStephen Lin2013-07-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186263 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.Joey Gouly2013-07-091-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185929 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.Joey Gouly2013-07-091-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185926 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.Joey Gouly2013-07-091-0/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185922 91177308-0d34-0410-b5e6-96231b3b80d8
* CEHCK->CHECK typo fix.Eric Christopher2013-07-081-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185875 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up whitespace.Eric Christopher2013-07-081-36/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185874 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MC support for the v8fp instructions: vmaxnm and vminnm.Joey Gouly2013-07-061-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185767 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'not' in front of a command that is expected to fail.Rafael Espindola2013-07-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185659 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} ↵Joey Gouly2013-07-041-0/+18
| | | | | | | | | | instructions. This adds a new decoder table/namespace 'VFPV8', as these instructions have their top 4 bits as 0b1111, while other Thumb instructions have 0b1110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.Joey Gouly2013-07-042-0/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying ↵Tilmann Scheller2013-07-031-0/+2
| | | | | | | | | | | | | | | | certain Thumb2 add immediate T3 encodings. Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding. The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process. This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly. Fixes <rdar://problem/14224440>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefix failing commands with not to make clear they are expected to fail.Rafael Espindola2013-07-037-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185554 91177308-0d34-0410-b5e6-96231b3b80d8
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-032-5/+11
| | | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM EHABI compact model 1 and 2 without handlerdata.Logan Chien2013-07-021-1/+1
| | | | | | | | | | | | | | | | According to ARM EHABI section 9.2, if the __aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is used, then the handler data must be emitted after the unwind opcodes. The handler data consists of several words, and should be terminated by zero. In case that the .handlerdata directive is not specified by the programmer, we should emit zero to terminate the handler data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185422 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMAsmParser] Sort the ARM register lists based on the encoding value, not theChad Rosier2013-07-012-21/+21
| | | | | | | tablegen enum values. This should be the last fix due to fallout from r185094. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185379 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix pseudo-instructions for SRS (Store Return State).Tilmann Scheller2013-06-282-20/+20
| | | | | | | | | | | | | | | The mapping between SRS pseudo-instructions and SRS native instructions was incorrect, the correct mapping is: srsfa -> srsib srsea -> srsia srsfd -> srsdb srsed -> srsda This fixes <rdar://problem/14214734>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185155 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve the compression of the tablegen DiffLists by introducing a new sortChad Rosier2013-06-271-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | algorithm when assigning EnumValues to the synthesized registers. The current algorithm, LessRecord, uses the StringRef compare_numeric function. This function compares strings, while handling embedded numbers. For example, the R600 backend registers are sorted as follows: T1 T1_W T1_X T1_XYZW T1_Y T1_Z T2 T2_W T2_X T2_XYZW T2_Y T2_Z In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2 have an EnumValue offset of 6 from one another. However, in other parts of the register bank, the scaling factors are different: dEnum/dN = 5: KC0_128_W KC0_128_X KC0_128_XYZW KC0_128_Y KC0_128_Z KC0_129_W KC0_129_X KC0_129_XYZW KC0_129_Y KC0_129_Z The diff lists do not work correctly because different kinds of registers have different 'scaling factors'. This new algorithm, LessRecordRegister, tries to enforce a scaling factor of 1. For example, the registers are now sorted as follows: T1 T2 T3 ... T0_W T1_W T2_W ... T0_X T1_X T2_X ... KC0_128_W KC0_129_W KC0_130_W ... For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I did see a few small regressions, but the differences were on the order of a few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even greater wins for targets with larger register files. Patch reviewed by Jakob. rdar://14006013 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185094 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-264-0/+65
| | | | | | | | | | Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: allow predicated barriers in Thumb modeTim Northover2013-06-262-0/+33
| | | | | | | The barrier instructions are only "always-execute" in ARM mode, they can quite happily sit inside an IT block in Thumb. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix thumb1 nop decodingAmaury de la Vieuville2013-06-242-2/+2
| | | | | | | In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8. However the disassembler should not use this alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184703 91177308-0d34-0410-b5e6-96231b3b80d8
* This reverts r155000.Joey Gouly2013-06-201-0/+2
| | | | | | | | | | The cdp2 instruction should have the same restrictions as cdp on the co-processor registers. VFP instructions on v8/AArch32 share the same encoding space as cdp2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184445 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add optional datatype suffix to NEON mvn asm syntax.Jim Grosbach2013-06-181-0/+39
| | | | | | rdar://14194152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184244 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the arm assembler to support this from the v7c spec:Kevin Enderby2013-06-182-0/+5
| | | | | | | | | | | | | | | | "When assembling to the ARM instruction set, the .N qualifier produces an assembler error and the .W qualifier has no effect." In the pre-matcher handler in the asm parser the ".w" (wide) qualifier when in ARM mode is now discarded. And an error message is now produced when the ".n" (narrow) qualifier is used in ARM mode. Test cases for these were added. rdar://14064574 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184224 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix literal load with positive offset encodingAmaury de la Vieuville2013-06-181-1/+20
| | | | | | | | | | | | When using a positive offset, literal loads where encoded as if it was negative, because: - The sign bit was not assigned to an operand - The addrmode_imm12 operand was not encoding the sign bit correctly This patch also makes the assembler look at the .w/.n specifier for loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
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