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* Update to LLVM 3.5a.Stephen Hines2014-04-241-0/+3
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* [mips] Fix FP conditional move instructions to have explicit FP condition codeAkira Hatanaka2013-07-261-0/+18
| | | | | | | | register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix FP branch instructions to have explicit FP condition code registerAkira Hatanaka2013-07-261-0/+6
| | | | | | | | operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Print instructions "beq", "bne" and "or" using assembler pseudoAkira Hatanaka2013-07-261-0/+6
| | | | | | | | | | | | instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Increase the number of floating point control registers available to 32.Akira Hatanaka2013-07-011-4/+4
| | | | | | | | | Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getRegChad Rosier2013-06-261-4/+4
| | | | | | | | function to lookup the proper tablegen'ed register enumeration. Previously, it was using the encoded value directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
* Use object file specific section type for initial text sectionNico Rieck2013-04-141-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-171-0/+6
| | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting 172579Jack Carter2013-01-161-6/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
* Akira,Jack Carter2013-01-161-0/+6
| | | | | | | | | | | | | | Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.Akira Hatanaka2012-07-121-162/+138
| | | | | | | | Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160143 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r158846.Akira Hatanaka2012-07-091-43/+49
| | | | | | | | Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
* revert r159851.Akira Hatanaka2012-07-061-49/+43
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r158846.Akira Hatanaka2012-07-061-43/+49
| | | | | | | Include file MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r158846.Akira Hatanaka2012-06-201-49/+43
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
* In MipsDisassembler.cpp, instead of defining register class tables, use the onesAkira Hatanaka2012-06-201-43/+49
| | | | | | | | | | | | that are generated by TableGen and are already available in MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen. Also, fix bug in function DecodeAFGR64RegisterClass. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembler to MIPS. Akira Hatanaka2012-04-171-0/+424
| | | | | | | | Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r153924. Delete test/MC/Disassembler/Mips and ↵Akira Hatanaka2012-04-031-0/+0
| | | | | | lib/Target/Mips/Disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153926 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r153924. There were buildbot failures.Akira Hatanaka2012-04-031-424/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS disassembler support.Akira Hatanaka2012-04-031-0/+424
Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
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