aboutsummaryrefslogtreecommitdiffstats
path: root/test/MC/Disassembler
Commit message (Expand)AuthorAgeFilesLines
* Fix Bug 9386 - ARM disassembler failed to disassemble conditional bxJohnny Chen2011-05-221-0/+3
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immedi...Johnny Chen2011-05-181-0/+3
* Add tests for A8.6.110 NOP.Johnny Chen2011-04-272-0/+9
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) s...Johnny Chen2011-04-222-3/+6
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-151-0/+3
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-151-0/+11
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* inst...Johnny Chen2011-04-152-0/+16
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of opera...Johnny Chen2011-04-144-0/+33
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-0/+3
* Check for unallocated instruction encodings when disassembling Thumb Branch i...Johnny Chen2011-04-132-2/+13
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-131-0/+10
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as...Johnny Chen2011-04-132-0/+20
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was no...Johnny Chen2011-04-131-0/+3
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-122-0/+23
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-0/+3
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+10
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have it...Johnny Chen2011-04-121-1/+13
* Print out a debug message when the reglist fails the sanity check for Thumb L...Johnny Chen2011-04-121-0/+10
* Add one test case (svc).Johnny Chen2011-04-121-0/+3
* A8.6.16 BJohnny Chen2011-04-121-0/+10
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+9
* Fix the bug where the immediate shift amount for Thumb logical shift instruct...Johnny Chen2011-04-111-0/+6
* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag th...Johnny Chen2011-04-114-0/+34
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-0/+3
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-083-0/+38
* MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.Johnny Chen2011-04-082-0/+16
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-084-0/+50
* Add a VEXT test.Johnny Chen2011-04-071-0/+3
* Add sanity checking for invalid register encodings for signed/unsigned extend...Johnny Chen2011-04-072-0/+17
* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+11
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-072-0/+14
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+12
* The ARM disassembler was not recognizing USADA8 instruction. Need to add che...Johnny Chen2011-04-071-0/+3
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-0/+11
* A8.6.393Johnny Chen2011-04-061-0/+11
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-063-0/+16
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-061-0/+3
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-061-1/+4
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal...Johnny Chen2011-04-051-3/+6
* A7.3 register encodingJohnny Chen2011-04-052-1/+11
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-051-0/+9
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-051-0/+9
* The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.Johnny Chen2011-04-051-0/+3
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-052-4/+5
* LDRD now prints out two dst registers.Johnny Chen2011-04-051-1/+1
* Constants with multiple encodings (ARM):Johnny Chen2011-04-051-3/+3
* Check for invalid register encodings for UMAAL and friends where:Johnny Chen2011-04-051-0/+11
* Fix SRS/SRSW encoding bits.Johnny Chen2011-04-052-0/+24
* Fix incorrect alignment for NEON VST2b32_UPD.Johnny Chen2011-04-041-0/+3
* Fixed a bug in disassembly of STR_POST, where the immediate is the second ope...Johnny Chen2011-04-021-0/+3
generated by cgit v1.1 at 2024-09-09 03:49:55 +0000