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* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-172-0/+12
* reverting 172579Jack Carter2013-01-162-12/+0
* Akira,Jack Carter2013-01-162-0/+12
* Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si,...Craig Topper2013-01-062-10/+10
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-10/+0
* Add instruction encodings / disassembly support for l2r instructions.Richard Osborne2012-12-171-0/+32
* Add instruction encodings for PEEK and ENDIN.Richard Osborne2012-12-171-0/+6
* Add instruction encodings / disassembly support for rus instructions.Richard Osborne2012-12-171-0/+20
* Add instruction encodings for ZEXT and SEXT.Richard Osborne2012-12-171-0/+6
* Add instruction encodings / disassembly support for 2r instructions.Richard Osborne2012-12-171-0/+74
* Add instruction encodings / disassembly support for 0r instructions.Richard Osborne2012-12-171-0/+20
* Add tests for disassembly of 1r XCore instructions.Richard Osborne2012-12-162-0/+45
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-052-0/+15
* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-0/+11
* Make this test less sensitive.Eli Bendersky2012-11-261-4/+4
* Remove DOS line endings.Jakub Staszak2012-11-144-316/+316
* [mips] Fix disassembler test cases.Akira Hatanaka2012-11-024-24/+24
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-304-5/+7
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-291-0/+3
* Add support for annotated disassembly output for X86 and arm.Kevin Enderby2012-10-222-0/+13
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-062-2/+6
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) instru...Tim Northover2012-09-065-0/+93
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-061-0/+77
* ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.Jim Grosbach2012-08-132-8/+10
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ...Jiangning Liu2012-08-021-1/+11
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-022-33/+93
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-022-0/+8
* Make l/q suffixes on AVX forms of scalar convert instructions consistent with...Craig Topper2012-07-262-8/+8
* Make x86 asm parser to check for xmm vs ymm for index register in gather inst...Craig Topper2012-07-181-0/+5
* Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.Akira Hatanaka2012-07-128-760/+694
* Fix instruction description of VMOV (between two ARM core registers and two s...Richard Barton2012-07-101-1/+20
* Reverse assembler/disassembler operand order for gather instructions.Craig Topper2012-07-101-8/+8
* Reapply r158846.Akira Hatanaka2012-07-094-160/+172
* revert r159851.Akira Hatanaka2012-07-064-172/+160
* Reapply r158846.Akira Hatanaka2012-07-064-160/+172
* Fix the remaining TCL-style quotes found in the testsuite. This isChandler Carruth2012-07-027-7/+7
* Convert the uses of '|&' to use '2>&1 |' instead, which works on oldChandler Carruth2012-07-0269-71/+71
* Convert all tests using TCL-style quoting to use shell-style quoting.Chandler Carruth2012-07-0239-39/+39
* X86: add more GATHER intrinsics in LLVMManman Ren2012-06-291-1/+19
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-0/+6
* Revert r158846.Akira Hatanaka2012-06-204-172/+160
* In MipsDisassembler.cpp, instead of defining register class tables, use the onesAkira Hatanaka2012-06-204-160/+172
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-1/+10
* Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.Akira Hatanaka2012-05-311-0/+6
* Add intrinsics, code gen, assembler and disassembler support for the SSE4a ex...Benjamin Kramer2012-05-292-0/+36
* Added the missing bit definition for the 4th bit of the STR (post reg) instru...Silviu Baranga2012-05-112-0/+67
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-0/+8
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-0/+27
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-021-12/+0
* Missed some register numbers.Benjamin Kramer2012-04-271-3/+3