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* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-0/+4
| | | | Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-336/+336
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update to LLVM 3.5a.Stephen Hines2014-04-241-1/+1
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-141-9/+9
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some instructions that existed to provide aliases to the assembler. ↵Craig Topper2013-10-081-3/+3
| | | | | | Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to ↵Craig Topper2013-10-071-0/+56
| | | | | | | | | | register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192088 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, ↵Craig Topper2013-01-061-30/+30
| | | | | | | | | | | | | cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior. cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix. cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix. Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171668 91177308-0d34-0410-b5e6-96231b3b80d8
* Make l/q suffixes on AVX forms of scalar convert instructions consistent ↵Craig Topper2012-07-261-20/+20
| | | | | | with their non-AVX forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-181-0/+32
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverse assembler/disassembler operand order for gather instructions.Craig Topper2012-07-101-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: add more GATHER intrinsics in LLVMManman Ren2012-06-291-2/+26
| | | | | | | | | | | | | | | | Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-0/+8
| | | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some duplicate instructions that exist only to given different ↵Craig Topper2012-06-261-6/+6
| | | | | | mnemonics for the assembler. Use InstAlias instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159184 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-031-0/+768
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we correctly note the existence of an i8 immediate for vblendvps ↵Eli Friedman2011-12-151-0/+7
| | | | | | and friends, so we compute fixups correctly. PR11586. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
* The wrong relocation was being emitted for several SSSE3 instructions.Bruno Cardoso Lopes2011-09-201-0/+6
| | | | | | | This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen declaration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140184 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10949. Fix the encoding of VMOVPQIto64rr.Bruno Cardoso Lopes2011-09-191-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140098 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-write part of VEX encoding logic, to be more easy to read! Also fixBruno Cardoso Lopes2011-08-191-0/+4
| | | | | | a bug and add a testcase! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138123 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10677. Initial patch and idea by Peter Cooper but I've changed theBruno Cardoso Lopes2011-08-191-0/+16
| | | | | | implementation! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138029 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r133452: "Emit movq for 64-bit register to XMM register moves..."Bob Wilson2011-06-211-3/+3
| | | | | | | This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using the integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133524 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit movq for 64-bit register to XMM register moves, but continue to acceptNick Lewycky2011-06-201-3/+3
| | | | | | | movd when assembling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133452 91177308-0d34-0410-b5e6-96231b3b80d8
* move X86 subdir up a levelChris Lattner2010-10-011-0/+3318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115292 91177308-0d34-0410-b5e6-96231b3b80d8
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