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* Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,...Devang Patel2012-01-301-0/+3
* Intel syntax. Support .intel_syntax directive.Devang Patel2012-01-301-0/+7
* Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]Devang Patel2012-01-271-0/+2
* Intel Syntax: Extend special hand coded logic, to recognize special instructi...Devang Patel2012-01-241-0/+3
* Intel syntax: Robustify parsing of memory operand's displacement experssion.Devang Patel2012-01-231-2/+4
* Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]Devang Patel2012-01-231-1/+3
* Intel syntax: Parse segment registers.Devang Patel2012-01-231-0/+2
* Intel syntax: Robustify register parsing.Devang Patel2012-01-201-0/+2
* Intel syntax: Parse ... PTR [-8]Devang Patel2012-01-201-1/+2
* Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.Devang Patel2012-01-201-1/+4
* Post process 'and', 'sub' instructions and select better encoding, if available.Devang Patel2012-01-191-0/+8
* Intel syntax: There is no need to create unary expr for simple negative displ...Devang Patel2012-01-191-0/+4
* Post process 'xor', 'or' and 'cmp' instructions and select better encoding, i...Devang Patel2012-01-191-0/+22
* Process instructions after match to select alternative encoding which may be ...Devang Patel2012-01-181-0/+24
* Intel syntax: Fix parser match class to check memory operand size.Devang Patel2012-01-171-0/+2
* Intel syntax: Parse "BYTE PTR [RDX + RCX]"Devang Patel2012-01-171-0/+2
* Intel syntax: Do not unncessarily create plus expression for memory operand d...Devang Patel2012-01-171-0/+2
* Intel syntax: Ignore mnemonic aliases.Devang Patel2012-01-171-0/+8
* Intel syntax: Robustify memory operand parsing.Devang Patel2012-01-171-0/+8
* Add new test.Devang Patel2012-01-131-0/+10
* Remove test case, as Chris suggested.Devang Patel2012-01-121-23/+0
* Add test case to check intel syntax parsing.Devang Patel2012-01-121-0/+23
* Make sure we correctly note the existence of an i8 immediate for vblendvps an...Eli Friedman2011-12-151-0/+7
* XOP instructions and encoding tests.Jan Sjödin2011-12-121-0/+584
* Support for encoding all FMA4 instructions and tablegen patterns for allJan Sjödin2011-11-301-0/+378
* This patch contains support for encoding FMA4 instructions andBruno Cardoso Lopes2011-11-251-0/+13
* X86: alias cqo to cqto.Benjamin Kramer2011-11-241-0/+1
* Move test to the X86 directory, note the PR number and only run MC once.Rafael Espindola2011-10-311-0/+3
* Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix andKevin Enderby2011-10-273-0/+21
* Add X86 SARX, SHRX, and SHLX instructions.Craig Topper2011-10-231-0/+49
* Add X86 RORX instructionCraig Topper2011-10-231-0/+32
* Rename PEXTR to PEXT. Add intrinsics for BMI instructions.Craig Topper2011-10-191-8/+8
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-161-0/+32
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-161-0/+16
* Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does...Chris Lattner2011-10-161-0/+3
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3...Craig Topper2011-10-161-0/+16
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ...Craig Topper2011-10-151-0/+57
* Finish supporting cpp #file/line comments in assembler for error messages. SoKevin Enderby2011-10-121-0/+5
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 6...Craig Topper2011-10-072-4/+4
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This w...Craig Topper2011-10-062-0/+37
* The wrong relocation was being emitted for several SSSE3 instructions.Bruno Cardoso Lopes2011-09-201-0/+6
* Fix PR10949. Fix the encoding of VMOVPQIto64rr.Bruno Cardoso Lopes2011-09-191-0/+4
* Re-write part of VEX encoding logic, to be more easy to read! Also fixBruno Cardoso Lopes2011-08-191-0/+4
* Fix PR10677. Initial patch and idea by Peter Cooper but I've changed theBruno Cardoso Lopes2011-08-191-0/+16
* Reorder declarations of vmovmskp* and also put the necessary AVXBruno Cardoso Lopes2011-08-151-0/+8
* Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng2011-07-273-7/+14
* Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby2011-07-272-0/+39
* Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that aKevin Enderby2011-07-061-0/+6
* Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use...Eli Friedman2011-07-051-0/+16
* Recognize the xstorerng alias for VIA PadLock's xstore instruction.Joerg Sonnenberger2011-06-301-0/+4