| Commit message (Expand) | Author | Age | Files | Lines |
* | Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,... | Devang Patel | 2012-01-30 | 1 | -0/+3 |
* | Intel syntax. Support .intel_syntax directive. | Devang Patel | 2012-01-30 | 1 | -0/+7 |
* | Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] | Devang Patel | 2012-01-27 | 1 | -0/+2 |
* | Intel Syntax: Extend special hand coded logic, to recognize special instructi... | Devang Patel | 2012-01-24 | 1 | -0/+3 |
* | Intel syntax: Robustify parsing of memory operand's displacement experssion. | Devang Patel | 2012-01-23 | 1 | -2/+4 |
* | Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] | Devang Patel | 2012-01-23 | 1 | -1/+3 |
* | Intel syntax: Parse segment registers. | Devang Patel | 2012-01-23 | 1 | -0/+2 |
* | Intel syntax: Robustify register parsing. | Devang Patel | 2012-01-20 | 1 | -0/+2 |
* | Intel syntax: Parse ... PTR [-8] | Devang Patel | 2012-01-20 | 1 | -1/+2 |
* | Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax. | Devang Patel | 2012-01-20 | 1 | -1/+4 |
* | Post process 'and', 'sub' instructions and select better encoding, if available. | Devang Patel | 2012-01-19 | 1 | -0/+8 |
* | Intel syntax: There is no need to create unary expr for simple negative displ... | Devang Patel | 2012-01-19 | 1 | -0/+4 |
* | Post process 'xor', 'or' and 'cmp' instructions and select better encoding, i... | Devang Patel | 2012-01-19 | 1 | -0/+22 |
* | Process instructions after match to select alternative encoding which may be ... | Devang Patel | 2012-01-18 | 1 | -0/+24 |
* | Intel syntax: Fix parser match class to check memory operand size. | Devang Patel | 2012-01-17 | 1 | -0/+2 |
* | Intel syntax: Parse "BYTE PTR [RDX + RCX]" | Devang Patel | 2012-01-17 | 1 | -0/+2 |
* | Intel syntax: Do not unncessarily create plus expression for memory operand d... | Devang Patel | 2012-01-17 | 1 | -0/+2 |
* | Intel syntax: Ignore mnemonic aliases. | Devang Patel | 2012-01-17 | 1 | -0/+8 |
* | Intel syntax: Robustify memory operand parsing. | Devang Patel | 2012-01-17 | 1 | -0/+8 |
* | Add new test. | Devang Patel | 2012-01-13 | 1 | -0/+10 |
* | Remove test case, as Chris suggested. | Devang Patel | 2012-01-12 | 1 | -23/+0 |
* | Add test case to check intel syntax parsing. | Devang Patel | 2012-01-12 | 1 | -0/+23 |
* | Make sure we correctly note the existence of an i8 immediate for vblendvps an... | Eli Friedman | 2011-12-15 | 1 | -0/+7 |
* | XOP instructions and encoding tests. | Jan Sjödin | 2011-12-12 | 1 | -0/+584 |
* | Support for encoding all FMA4 instructions and tablegen patterns for all | Jan Sjödin | 2011-11-30 | 1 | -0/+378 |
* | This patch contains support for encoding FMA4 instructions and | Bruno Cardoso Lopes | 2011-11-25 | 1 | -0/+13 |
* | X86: alias cqo to cqto. | Benjamin Kramer | 2011-11-24 | 1 | -0/+1 |
* | Move test to the X86 directory, note the PR number and only run MC once. | Rafael Espindola | 2011-10-31 | 1 | -0/+3 |
* | Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and | Kevin Enderby | 2011-10-27 | 3 | -0/+21 |
* | Add X86 SARX, SHRX, and SHLX instructions. | Craig Topper | 2011-10-23 | 1 | -0/+49 |
* | Add X86 RORX instruction | Craig Topper | 2011-10-23 | 1 | -0/+32 |
* | Rename PEXTR to PEXT. Add intrinsics for BMI instructions. | Craig Topper | 2011-10-19 | 1 | -8/+8 |
* | Add X86 PEXTR and PDEP instructions. | Craig Topper | 2011-10-16 | 1 | -0/+32 |
* | Add X86 BZHI instruction as well as BMI2 feature detection. | Craig Topper | 2011-10-16 | 1 | -0/+16 |
* | Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does... | Chris Lattner | 2011-10-16 | 1 | -0/+3 |
* | Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3... | Craig Topper | 2011-10-16 | 1 | -0/+16 |
* | Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ... | Craig Topper | 2011-10-15 | 1 | -0/+57 |
* | Finish supporting cpp #file/line comments in assembler for error messages. So | Kevin Enderby | 2011-10-12 | 1 | -0/+5 |
* | Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 6... | Craig Topper | 2011-10-07 | 2 | -4/+4 |
* | Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This w... | Craig Topper | 2011-10-06 | 2 | -0/+37 |
* | The wrong relocation was being emitted for several SSSE3 instructions. | Bruno Cardoso Lopes | 2011-09-20 | 1 | -0/+6 |
* | Fix PR10949. Fix the encoding of VMOVPQIto64rr. | Bruno Cardoso Lopes | 2011-09-19 | 1 | -0/+4 |
* | Re-write part of VEX encoding logic, to be more easy to read! Also fix | Bruno Cardoso Lopes | 2011-08-19 | 1 | -0/+4 |
* | Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the | Bruno Cardoso Lopes | 2011-08-19 | 1 | -0/+16 |
* | Reorder declarations of vmovmskp* and also put the necessary AVX | Bruno Cardoso Lopes | 2011-08-15 | 1 | -0/+8 |
* | Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. | Evan Cheng | 2011-07-27 | 3 | -7/+14 |
* | Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates. | Kevin Enderby | 2011-07-27 | 2 | -0/+39 |
* | Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a | Kevin Enderby | 2011-07-06 | 1 | -0/+6 |
* | Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use... | Eli Friedman | 2011-07-05 | 1 | -0/+16 |
* | Recognize the xstorerng alias for VIA PadLock's xstore instruction. | Joerg Sonnenberger | 2011-06-30 | 1 | -0/+4 |