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* [ms-inline asm] Add support for .att_syntax directive.Chad Rosier2012-09-101-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163542 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix alignment of .comm and .lcomm on mingw32.Benjamin Kramer2012-09-071-0/+13
| | | | | | | | For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't use the same setting for both. Fix this by reintroducing the LCOMM enum. I verified this against mingw's gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163420 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial relocations test for the Mips standalone assembler.Jack Carter2012-09-071-0/+41
| | | | | | | | | This is not an exhaustive set, but something we can build on. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163419 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-073-4/+30
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163395 91177308-0d34-0410-b5e6-96231b3b80d8
* PR13754: llvm-mc/x86 crashes on .cfi directives without the % prefix for ↵Benjamin Kramer2012-09-071-0/+18
| | | | | | | | | registers. gas accepts this and it seems to be common enough to be worth supporting. This doesn't affect the parsing of reg operands outside of .cfi directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163390 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips standalone assembler aliased instruction support.Jack Carter2012-09-072-0/+27
| | | | | | | | | | | | | | | | The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips standalone assembler intial directive support.Jack Carter2012-09-071-0/+10
| | | | | | | | | | | | Actually these are just stubs for parsing the directives. Semantic support will come later. Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163364 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips standalone assembler fpu instruction support.Jack Carter2012-09-072-0/+166
| | | | | | | | | Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163363 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips standalone assembler memory instruction support.Jack Carter2012-09-061-0/+41
| | | | | | | | | | | This includes sb,sc,sh,sw,lb,lw,lbu,lh,lhu,ll,lw Test case included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163346 91177308-0d34-0410-b5e6-96231b3b80d8
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-062-2/+6
| | | | | | Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163323 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-065-0/+93
| | | | | | | | instructions. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163321 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct part of complex operand to encode VST1 alignment.Tim Northover2012-09-061-0/+77
| | | | | | Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163318 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific llvm assembler support for branch and jump instructions.Jack Carter2012-09-061-0/+64
| | | | | | | | | Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific llvm assembler support for ALU instructions. This includesJack Carter2012-09-051-0/+81
| | | | | | | | | register support. Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163268 91177308-0d34-0410-b5e6-96231b3b80d8
* The instruction DINS may be transformed into DINSU or DEXTM dependingJack Carter2012-08-311-0/+29
| | | | | | | | | | | | | | | | | | | | | | | on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163010 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix encoding of 'movd %xmm0, %rax'Jim Grosbach2012-08-311-0/+4
| | | | | | | The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v' prefix, resulting in mis-assembly of the vanilla movd instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162963 91177308-0d34-0410-b5e6-96231b3b80d8
* The instruction DEXT may be transformed into DEXTU or DEXTM dependingJack Carter2012-08-281-0/+28
| | | | | | | | | | | | | | | | | | | | | | | on the size of the extraction and its position in the 64 bit word. This patch allows support of the dext transformations with mips64 direct object output. 0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32 DINS The field is entirely contained in the right-most word of the doubleword 32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64 DINSM The field straddles the words of the doubleword 32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32 DINSU The field is entirely contained in the left-most word of the doubleword git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162782 91177308-0d34-0410-b5e6-96231b3b80d8
* Some instructions are passed to the assembler to beJack Carter2012-08-281-1/+4
| | | | | | | | | | | | | | transformed to the final instruction variant. An example would be dsrll which is transformed into dsll32 if the shift value is greater than 32. For direct object output we need to do this transformation in the codegen. If the instruction was inside branch delay slot, it was being missed. This patch corrects this oversight. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix mips' long branch pass.Akira Hatanaka2012-08-281-2/+5
| | | | | | | | | | Instructions emitted to compute branch offsets now use immediate operands instead of symbolic labels. This change was needed because there were problems when R_MIPS_HI16/LO16 relocations were used to make shared objects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162731 91177308-0d34-0410-b5e6-96231b3b80d8
* Add option disable-mips-delay-filler. Turn on mips' delay slot filler byAkira Hatanaka2012-08-223-4/+4
| | | | | | | | | default. Patch by Carl Norum. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162339 91177308-0d34-0410-b5e6-96231b3b80d8
* For mips64 switch statements in subroutines could generate Jack Carter2012-08-221-0/+39
| | | | | | | | | | | | | | within the codegen EK_GPRel64BlockAddress. This was not supported for direct object output and resulted in an assertion. This change adds support for EK_GPRel64BlockAddress for direct object. One fallout from this is to turn on rela relocations for mips64 to match gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162334 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix macros arguments with an underscore, dot or dollar in them. This is basedRafael Espindola2012-08-211-0/+21
| | | | | | on a patch by Andy/PaX. I added the support for dot and dollar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162298 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the wording in of the "expected identifier" error in the .macro directiveRafael Espindola2012-08-211-0/+9
| | | | | | | consistent with the other "expected identifier" errors. Extracted from the Andy/PaX patch. I added the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162291 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.Jim Grosbach2012-08-132-8/+10
| | | | | | These tests weren't actually being run before (missing ':' after CHECK). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161800 91177308-0d34-0410-b5e6-96231b3b80d8
* Give this test an explicit triple.Nick Lewycky2012-08-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161740 91177308-0d34-0410-b5e6-96231b3b80d8
* When emitting the PC range in an FDE, use the same data encoding for both endsNick Lewycky2012-08-121-0/+28
| | | | | | | of the range. Fixes PR13581! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161739 91177308-0d34-0410-b5e6-96231b3b80d8
* Another 32 to 64 bit sign extension bug.Jack Carter2012-08-091-4/+9
| | | | | | | The fields in the td definition were switched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161607 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/MC/COFF/seh.s: Fixup corresponding to r161487.NAKAMURA Takumi2012-08-081-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161489 91177308-0d34-0410-b5e6-96231b3b80d8
* Add `.pushsection', `.popsection', and `.previous' directives to Darwin ASM.Bill Wendling2012-08-082-0/+29
| | | | | | | | | | | | | | | | | | | | | There are situations where inline ASM may want to change the section -- for instance, to create a variable in the .data section. However, it cannot do this without (potentially) restoring to the wrong section. E.g.: asm volatile (".section __DATA, __data\n\t" ".globl _fnord\n\t" "_fnord: .quad 1f\n\t" ".text\n\t" "1:" :::); This may be wrong if this is inlined into a function that has a "section" attribute. The user should use `.pushsection' and `.popsection' here instead. The addition of `.previous' is added for completeness. <rdar://problem/12048387> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161477 91177308-0d34-0410-b5e6-96231b3b80d8
* The define for 64 bit sign extension neglected to Jack Carter2012-08-071-0/+15
| | | | | | | | | | | | | | | | | | | | | initialize fields of the class that it used. The result was nonsense code. Before: 0000000000000000 <foo>: 0: 00441100 0x441100 4: 03e00008 jr ra 8: 00000000 nop After: 0000000000000000 <foo>: 0: 00041000 sll v0,a0,0x0 4: 03e00008 jr ra 8: 00000000 nop git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161377 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64 Jack Carter2012-08-061-0/+18
| | | | | | | | | | | were using a class defined for 32 bit instructions and thus the instruction was for addiu instead of daddiu. This was corrected by adding the instruction opcode as a field in the base class to be filled in by the defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161359 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips relocations R_MIPS_HIGHER and R_MIPS_HIGHEST.Jack Carter2012-08-061-0/+27
| | | | | | | | | | | | | | | These 2 relocations gain access to the highest and the second highest 16 bits of a 64 bit object. R_MIPS_HIGHER %higher(A+S) The %higher(x) function is [ (((long long) x + 0x80008000LL) >> 32) & 0xffff ]. R_MIPS_HIGHEST %highest(A+S) The %highest(x) function is [ (((long long) x + 0x800080008000LL) >> 48) & 0xffff ]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161348 91177308-0d34-0410-b5e6-96231b3b80d8
* Support fpv4 for ARM Cortex-M4.Jiangning Liu2012-08-021-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161163 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-022-1/+23
| | | | | | index issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-024-33/+235
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-024-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep empty assembly macro argument values in the middle of the list.Jim Grosbach2012-07-301-0/+12
| | | | | | | | | | | | | | | | | | | Empty macro arguments at the end of the list should be as-if not specified at all, but those in the middle of the list need to be kept so as not to screw up the positional numbering. E.g.: .macro foo foo_-bash___: nop .endm foo 1, 2, 3, 4 foo 1, , 3, 4 Should create two labels, "foo_1_2_3_4" and "foo_1__3_4". rdar://11948769 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161002 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in ARMMachObjectWriter::RecordRelocation() in ARMMachObjectWriter.cppKevin Enderby2012-07-301-0/+44
| | | | | | | | | | where the other_half of the movt and movw relocation entries needs to get set and only with the 16 bits of the other half. rdar://10038370 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160978 91177308-0d34-0410-b5e6-96231b3b80d8
* Make l/q suffixes on AVX forms of scalar convert instructions consistent ↵Craig Topper2012-07-264-36/+36
| | | | | | with their non-AVX forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-183-0/+39
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
* Doubleword Shift Left Logical Plus 32Jack Carter2012-07-161-0/+45
| | | | | | | | | | | | | | | | | | | | | | Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips specific relocation R_MIPS_GOT_DISP Jack Carter2012-07-131-0/+18
| | | | | | | | | | | is used in cases where global symbols are directly represented in the GOT and we use an offset into the global offset table. This patch adds direct object support for R_MIPS_GOT_DISP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160183 91177308-0d34-0410-b5e6-96231b3b80d8
* test case for revision 160084: Alignment filling between Mips function unitsJack Carter2012-07-131-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160177 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.Akira Hatanaka2012-07-128-760/+694
| | | | | | | | Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160143 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-102-1/+41
| | | | | | single-precision resiters) (and do it properly this time! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverse assembler/disassembler operand order for gather instructions.Craig Topper2012-07-102-16/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-091-21/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r158846.Akira Hatanaka2012-07-094-160/+172
| | | | | | | | Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-091-0/+21
| | | | | | single-precision resiters) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent ARM assembler from losing a right shift by #32 applied to a registerRichard Barton2012-07-091-0/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
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