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* Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga2012-04-181-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the bahavior of the disassembler when decoding unpredictable mrs ↵Silviu Baranga2012-04-181-0/+18
| | | | | | instructions on ARM. Now the diasassembler emmits warnings instead of errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ↵Silviu Baranga2012-04-182-0/+17
| | | | | | disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed decoding for the ARM cdp2 instruction. The restriction on the ↵Silviu Baranga2012-04-181-0/+3
| | | | | | coprocessor number was removed for this instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
* Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM ↵Silviu Baranga2012-04-181-0/+30
| | | | | | instructions in the disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154999 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembler to MIPS. Akira Hatanaka2012-04-178-0/+2042
| | | | | | | | Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)Kevin Enderby2012-04-172-0/+75
| | | | | | | | instructions with writebacks. And add test a case for all opcodes handed by DecodeVLD2DupInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM two-operand forms for vhadd and vhsub instructions.Jim Grosbach2012-04-162-0/+53
| | | | | | rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
* MC assembly parser handling for trailing comma in macro instantiation.Jim Grosbach2012-04-161-0/+24
| | | | | | | | | A trailing comma means no argument at all (i.e., as if the comma were not present), not an empty argument to the invokee. rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154863 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch fixes 3 problems:Akira Hatanaka2012-04-161-10/+10
| | | | | | | | | | | | | | | 1. CHECKNEXT was used instead of CHECK-NEXT which caused the line to be ignored which in turn hid the next 2 problems: 2. ('sh_offset', 0x{{{[0-9,a-f]+}}) had one too many leading curly braces and failed to do it's job of accepting all hex digits and: 3. The check for the hex values for the code instructions didn't account for blank separators. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154842 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly two-operand forms for VRSHL.Jim Grosbach2012-04-161-0/+35
| | | | | | rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154840 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Test formatting.Jim Grosbach2012-04-161-53/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154839 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not add offset in applyFixup. This has already been accounted for in Value. Akira Hatanaka2012-04-161-0/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154838 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM two-operand aliases for VRHADD instructions.Jim Grosbach2012-04-161-0/+27
| | | | | | rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154832 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Testcase formatting.Jim Grosbach2012-04-161-13/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154831 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -disassemble support for -show-inst and -show-encode capability llvm-mc. ↵Richard Barton2012-04-161-1/+1
| | | | | | | | | Also refactor so all MC paraphernalia are created once for all uses as much as possible. The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154809 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby2012-04-111-0/+13
| | | | | | | of a VST instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VUZP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11222366 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154511 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VZIP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11221911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154505 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-111-1/+1
| | | | | | | | | | | | predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
* Add retw and lretw instructions. Also, fix Intel syntax parsing for allCharles Davis2012-04-114-0/+31
| | | | | | | ret instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM disassembly of VLD instructions with writebacks.  And add test a caseKevin Enderby2012-04-112-0/+364
| | | | | | | for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM add missing Thumb1 two-operand aliases for shift-by-immediate.Jim Grosbach2012-04-111-0/+18
| | | | | | rdar://11222742 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154457 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-112-0/+87
| | | | | | | | | | | 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM fix cc_out operand handling for t2SUBrr instructions.Jim Grosbach2012-04-101-0/+12
| | | | | | | | | | | | We were incorrectly conflating some add variants which don't have a cc_out operand with the mirroring sub encodings, which do. Part of the awesome non-orthogonality legacy of thumb1. Similarly, handling of add/sub of an immediate was sometimes incorrectly removing the cc_out operand for add/sub register variants. rdar://11216577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the tests that were supposed to go with r153935 that I forgot svn addCraig Topper2012-04-062-0/+73
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154165 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly aliases for add negative immediates using sub.Jim Grosbach2012-04-051-0/+4
| | | | | | | | | | 'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out. Thumb1 aliases for adding a negative immediate to the stack pointer, also. rdar://11192734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154123 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for unpredictable ADC/SBC instructions on ARM, and also fixed ↵Silviu Baranga2012-04-051-0/+17
| | | | | | some corner cases involving the PC register as an operand for these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for handling unpredictable arithmetic instructions on ARM.Silviu Baranga2012-04-052-12/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly aliases for two-operand V[R]SHR instructions.Jim Grosbach2012-04-051-0/+70
| | | | | | rdar://11189467 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing for 'msr' plain 'cpsr' operand.Jim Grosbach2012-04-051-0/+2
| | | | | | | | Plain 'cpsr' is an alias for 'cpsr_fc'. rdar://11153753 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-032-0/+780
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r153924. Delete test/MC/Disassembler/Mips and ↵Akira Hatanaka2012-04-038-0/+0
| | | | | | lib/Target/Mips/Disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153926 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r153924. There were buildbot failures.Akira Hatanaka2012-04-038-2042/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS disassembler support.Akira Hatanaka2012-04-038-0/+2042
| | | | | | | Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial 64 bit direct object support.Akira Hatanaka2012-04-021-5/+30
| | | | | | | | | | | | This patch allows llvm to recognize that a 64 bit object file is being produced and that the subsequently generated ELF header has the correct information. The test case checks for both big and little endian flavors. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153889 91177308-0d34-0410-b5e6-96231b3b80d8
* Added fix in TableGen instruction decoder generation. The decoder now breaks ↵Silviu Baranga2012-04-021-0/+15
| | | | | | for every leaf node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153874 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach2012-03-301-2/+5
| | | | | | | | When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg, we want to use the non-negated form to make sure we prefer the normal encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM encoding for VSWP got the second operand incorrect.Jim Grosbach2012-03-301-0/+7
| | | | | | | | | Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach2012-03-301-0/+8
| | | | | | | | | For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2 can be used for this syntax. Prefer the narrow encoding when possible. rdar://11156277 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing needs to be paranoid about negative immediates.Jim Grosbach2012-03-301-1/+4
| | | | | | | | Make sure to treat immediates as unsigned when doing relative comparisons. rdar://11153621 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy2012-03-303-2/+28
| | | | | | | | | | fixup_arm_condbranch. Patch by Tim Northover! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly 'cmp lr, #0' should not encode using 'cmn'.Jim Grosbach2012-03-291-0/+2
| | | | | | | | | The CMP->CMN alias was matching for an immediate of zero when it should only match for negative values. rdar://11129224 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.Richard Barton2012-03-281-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153573 91177308-0d34-0410-b5e6-96231b3b80d8
* Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnuEli Bendersky2012-03-2511-88/+11
| | | | | | | | | | | | | | | | | | * Removed test/lib/llvm.exp - it is no longer needed * Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files left in the test suite so this code is no longer required. test/lit.cfg is now much shorter and clearer * Removed a lot of duplicate code in lit.local.cfg files that need access to the root configuration, by adding a "root" attribute to the TestingConfig object. This attribute is dynamically computed to provide the same information as was previously provided by the custom getRoot functions. * Documented the config.root attribute in docs/CommandGuide/lit.pod git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
* Added soft fail checks for the disassembler when decoding some corner cases ↵Silviu Baranga2012-03-223-2/+21
| | | | | | of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
* Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or ↵Silviu Baranga2012-03-221-0/+22
| | | | | | LDRSHT instruction on ARM git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
* Added soft fail cases for the disassembler when decoding MUL instructions on ↵Silviu Baranga2012-03-221-0/+17
| | | | | | ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add testKevin Enderby2012-03-212-0/+368
| | | | | | | case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153218 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix generation of the address size override prefix. Add assertions forJoerg Sonnenberger2012-03-211-0/+13
| | | | | | | | the invalid cases. At least 16bit operand in 64bit mode is currently not rejected in the parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153166 91177308-0d34-0410-b5e6-96231b3b80d8
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