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* Use std::list so that we have a stable iterator.Rafael Espindola2013-05-211-3/+2
* [mips] Rename option to make it compatible with gcc.Akira Hatanaka2013-05-211-1/+1
* [mips] Add instruction selection patterns for blez and bgez.Akira Hatanaka2013-05-212-1/+37
* [NVPTX] Add @llvm.nvvm.sqrt.f() intrinsicJustin Holewinski2013-05-211-0/+7
* Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.Justin Holewinski2013-05-212-0/+33
* [msan] A no-op implementation of VarArg handling.Evgeniy Stepanov2013-05-212-0/+16
* X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the s...Benjamin Kramer2013-05-211-2/+8
* [SystemZ] Tighten branch testsRichard Sandiford2013-05-2185-442/+442
* DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0...Benjamin Kramer2013-05-211-0/+16
* Add checks that the proper predeined stubs are being called to the test case.Reed Kotler2013-05-211-0/+58
* Dwarf: use a single line table to generate assembly when .loc is used.Manman Ren2013-05-211-0/+6
* Add some additional functions to the list of helper functions forReed Kotler2013-05-211-0/+67
* PR14606: Debug Info for namespace aliases/DW_TAG_imported_moduleDavid Blaikie2013-05-201-29/+49
* add polly to check-allSebastian Pop2013-05-201-0/+9
* [mips] Add (setne $lhs, 0) instruction selection pattern.Akira Hatanaka2013-05-201-0/+10
* [mips] Trap on integer division by zero.Akira Hatanaka2013-05-202-11/+41
* [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a s...Justin Holewinski2013-05-201-0/+37
* R600: Fix rotr.ll on non-asserts buildsTom Stellard2013-05-201-6/+2
* R600/SI: Add pattern for rotrTom Stellard2013-05-201-9/+19
* R600: Swap the legality of rotl and rotrTom Stellard2013-05-201-0/+29
* R600/SI: Add patterns for 64-bit shift operationsTom Stellard2013-05-201-0/+3
* VSTn instructions have a number of encoding constraints which are not impleme...Mihai Popa2013-05-202-4/+45
* Q registers are encoded in fields of the same length as D registers. As Q reg...Mihai Popa2013-05-201-2/+2
* [SystemZ] Add long branch passRichard Sandiford2013-05-206-3/+200
* [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputsJustin Holewinski2013-05-201-0/+25
* [NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need...Justin Holewinski2013-05-202-0/+37
* PR15868 fix.Stepan Dyatkovskiy2013-05-203-8/+64
* Disable remote MCJIT on pre-v6 ARMRenato Golin2013-05-201-0/+11
* Also expand 64-bit bitcasts.Jakob Stoklund Olesen2013-05-201-0/+16
* Implement spill and fill of I64Regs.Jakob Stoklund Olesen2013-05-201-0/+8
* Mark i64 SETCC as expand so it is turned into a SELECT_CC.Jakob Stoklund Olesen2013-05-201-0/+10
* Don't use %g0 to materialize 0 directly.Jakob Stoklund Olesen2013-05-192-1/+12
* Select i64 values with %icc conditions.Jakob Stoklund Olesen2013-05-191-0/+11
* Add floating point selects on %xcc predicates.Jakob Stoklund Olesen2013-05-191-0/+22
* Implement SPselectfcc for i64 operands.Jakob Stoklund Olesen2013-05-191-0/+11
* [Sparc] Rearrange integer registers' allocation order so that register alloca...Venkatraman Govindaraju2013-05-191-1/+1
* Handle i64 FrameIndex nodes in SPARC v9 mode.Jakob Stoklund Olesen2013-05-191-0/+10
* Invalidate instruction cache when setting memory to be executable.Tim Northover2013-05-195-15/+4
* Temporarily disable this test because it is failing when using libc++.Bob Wilson2013-05-191-2/+3
* Move the remaining simplify-libcalls tests to instcombine, merging most of th...Benjamin Kramer2013-05-1912-138/+137
* Unsupported remote JIT on ARMRenato Golin2013-05-189-6/+17
* isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.David Majnemer2013-05-181-0/+14
* LoopVectorize: Handle single edge PHIsArnold Schwaighofer2013-05-181-0/+22
* Check InlineAsm clobbers in PPCCTRLoopsHal Finkel2013-05-181-0/+38
* X86: Bad peephole interaction between adc, MOV32r0David Majnemer2013-05-181-0/+27
* Support unaligned load/store on more ARM targetsJF Bastien2013-05-172-130/+147
* Convert obj2yaml to use yamlio.Rafael Espindola2013-05-171-96/+78
* R600: Lower int_load_input to copyFromReg instead of Register nodeVincent Lejeune2013-05-171-0/+121
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-1715-17/+19
* R600: Use depth first scheduling algorithmVincent Lejeune2013-05-172-2/+2