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* Emit cross regclass register moves for thumb2.Anton Korobeynikov2009-07-161-0/+35
* Assume an inline asm might be a call, so we getDale Johannesen2009-07-161-1/+1
* Emit line numbers in asm comments when available.David Greene2009-07-161-0/+27
* Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm ope...Jakob Stoklund Olesen2009-07-161-0/+16
* Changed my mind. We now allow remat of instructions whose defs have subreg in...Evan Cheng2009-07-161-4/+1
* this should be xfailed on darwin. Darwin doesn't use the libstdc++ in the ll...Chris Lattner2009-07-161-0/+1
* With recent MC changes, RIP base register is explicitly modeled. Make sure we...Evan Cheng2009-07-161-0/+102
* Fill in some holes in ScalarEvolution's loop iteration conditionDan Gohman2009-07-161-0/+38
* Make xfail properAnton Korobeynikov2009-07-161-1/+1
* Temporary disable 16 bit bswapAnton Korobeynikov2009-07-161-0/+1
* Add bswap patternsAnton Korobeynikov2009-07-161-0/+48
* Fix logic inversion for RI-mode address selectionAnton Korobeynikov2009-07-161-0/+32
* Unbreak the testAnton Korobeynikov2009-07-161-1/+2
* Expand 32-bit bitconverts via memoryAnton Korobeynikov2009-07-161-0/+15
* Fix incomin arg stack frame offset in case we need to generate stack frameAnton Korobeynikov2009-07-161-0/+22
* Revert the commit, it just hides the real bugAnton Korobeynikov2009-07-167-182/+14
* Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension ...Anton Korobeynikov2009-07-167-14/+182
* Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide...Anton Korobeynikov2009-07-162-5/+5
* Implement 'large' PIC modelAnton Korobeynikov2009-07-162-0/+56
* Implement shifts properly (hopefilly - finally!)Anton Korobeynikov2009-07-161-0/+25
* Properly handle divides. As a bonus - implement memory versions of them.Anton Korobeynikov2009-07-162-4/+68
* 32 bit shifts have only 12 bit displacementsAnton Korobeynikov2009-07-161-0/+27
* Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.Anton Korobeynikov2009-07-161-1/+16
* Add support for 12 bit displacementsAnton Korobeynikov2009-07-163-3/+132
* Emit proper lowering of load from arg stack slotAnton Korobeynikov2009-07-161-0/+19
* Implement dynamic allocasAnton Korobeynikov2009-07-161-0/+14
* Add jump tablesAnton Korobeynikov2009-07-161-0/+39
* Add rotatesAnton Korobeynikov2009-07-161-0/+13
* Add patterns for integer negateAnton Korobeynikov2009-07-162-0/+15
* Provide proper patterns for and with imm instructions. Tune the tests accordi...Anton Korobeynikov2009-07-167-14/+13
* Add 32 bit and reg-imm and disable invalid patterns for nowAnton Korobeynikov2009-07-167-10/+25
* Add z9 and z10 target processors. Mark z10-only instructions as such.Anton Korobeynikov2009-07-161-3/+3
* Proper lower 'small' resultsAnton Korobeynikov2009-07-161-0/+12
* Completel forgot about unconditional branchesAnton Korobeynikov2009-07-161-0/+18
* Lower addresses of globalsAnton Korobeynikov2009-07-161-0/+23
* Test (incomplete) for easy mulsAnton Korobeynikov2009-07-161-0/+29
* Provide "wide" muls and divs/remsAnton Korobeynikov2009-07-161-0/+55
* Tests for cmp / br_cc / select_ccAnton Korobeynikov2009-07-165-0/+570
* Emit callee-saved regs spills / restoresAnton Korobeynikov2009-07-162-2/+2
* Some preliminary call loweringAnton Korobeynikov2009-07-162-0/+29
* Prologue / epilogue emissionAnton Korobeynikov2009-07-161-0/+1
* Add simple frame index eliminationAnton Korobeynikov2009-07-162-0/+28
* Provide proper test :)Anton Korobeynikov2009-07-161-10/+9
* Add address computation stuffAnton Korobeynikov2009-07-161-0/+12
* Add mem-imm storesAnton Korobeynikov2009-07-161-0/+35
* Add stores and truncstoresAnton Korobeynikov2009-07-161-0/+67
* Add patterns for various extloadsAnton Korobeynikov2009-07-161-0/+75
* Add shifts and reg-imm address matchingAnton Korobeynikov2009-07-161-0/+121
* Add bunch of 32-bit patterns... Uffff :)Anton Korobeynikov2009-07-1612-0/+412
* Add tests for fixes I committed earlier to the C++ FE.Rafael Espindola2009-07-162-0/+22
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