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* [Sparc] Implements exception handling in SPARC with DwarfCFI.Venkatraman Govindaraju2013-09-261-0/+112
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191432 91177308-0d34-0410-b5e6-96231b3b80d8
* Implements parsing and emitting of .cfi_window_save in MC.Venkatraman Govindaraju2013-09-262-0/+66
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191431 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-262-15/+1345
| | | | | | | Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Allow partial fills in writeNopData()David Majnemer2013-09-261-1/+4
| | | | | | | | | | | | | | | | | | | When asked to pad an irregular number of bytes, we should fill with zeros. This is consistent with the behavior specified in the AIX Assembler Language Reference as well as other LLVM and binutils assemblers. N.B. There is a small deviation from binutils' PPC assembler: when handling pads which are greater than 4 bytes but not mod 4, binutils will not emit any NOP sequences at all and only use zeros. This may or may not be a bug but there is no excellent rationale as to why that behavior is important to emulate. If that behavior is needed, we can change writeNopData() to behave in the same way. This fixes PR17352. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191426 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Add support for fctid and fctiwDavid Majnemer2013-09-261-4/+8
| | | | | | | | | | Encodings were checked against the Power ISA documents and double checked against binutils. This fixes PR17350. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191419 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-261-0/+720
| | | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191415 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission for 2RF instructions.Jack Carter2013-09-251-0/+90
| | | | | | | Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191413 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-251-0/+12
| | | | | | | | | | | In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR 17368: disable vector mul distribution for square of add/sub for ARMWeiming Zhao2013-09-251-0/+11
| | | | | | | | | | | | | | | | | | | | | Generally, it is desirable to distribute (a + b) * c to a*c + b*c for ARM with VMLx forwarding, where a, b and c are vectors. However, for (a + b)*(a + b), distribution will result in one extra instruction. With distribution: x = a + b (add) y = a * x (mul) z = y + b * y (mla) Without distribution: x = a + b (add) z = x * x (mul) This patch checks if a mul is a square of add/sub. If yes, skip distribution. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191410 91177308-0d34-0410-b5e6-96231b3b80d8
* Unify pubsection/gnu pubsection printing.Eric Christopher2013-09-251-7/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191407 91177308-0d34-0410-b5e6-96231b3b80d8
* Test commit. Removed trailing whitespace.Josh Magee2013-09-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191402 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bad typo in the inline assembly code for mips16 pic fp stubsReed Kotler2013-09-252-12/+33
| | | | | | | | | and make one cosmetic cleanup to make it look the same as gcc in this area; adjusting test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191400 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DAGCombiner how to canonicalize dags according to the ruleAndrea Di Biagio2013-09-251-0/+181
| | | | | | | | | | | | | (shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)). The rule only triggers when there are no other uses of the zext to avoid materializing more instructions. This helps the DAGCombiner understand that the shl/shr sequence can then be converted into an and instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191393 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorize: Put horizontal reductions feeding a store under separate flagArnold Schwaighofer2013-09-251-8/+10
| | | | | | | Put them under a separate flag for experimentation. They are more likely to interfere with loop vectorization which happens later in the pass pipeline. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191371 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add support for treating $ as a reference to the PCDavid Majnemer2013-09-251-0/+5
| | | | | | | | | | | | | | | | | | The binutils assembler supports a mode called DOLLAR_DOT which treats the dollar sign token as a reference to the current program counter if the dollar sign doesn't precede a constant or identifier. This commit adds a new MCAsmInfo flag stating whether or not a given target supports this interpretation of the dollar sign token; by default, this flag is not enabled. Further, enable this flag for PPC. The system assembler for AIX and binutils both support using the dollar sign in this manner. This fixes PR17353. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191368 91177308-0d34-0410-b5e6-96231b3b80d8
* [PR16882] Ignore noreturn definitions when setting isPhysRegUsed.Quentin Colombet2013-09-251-0/+38
| | | | | | | | | | | | | | | | | | PEI inserts a save/restore sequence for the link register, according to the information it gets from the MachineRegisterInfo. MachineRegisterInfo is populated by the VirtRegMap pass. This pass was not aware of noreturn calls and was registering the definitions of these calls the same way as regular operations. Modify VirtRegPass so that it does not set the isPhysRegUsed information for registers only defined by noreturn calls. The rational is that a noreturn call is the "last instruction" of the program (if it returns the behavior is undefined), so everything that is defined by it cannot be used and will not interfere with anything else. Therefore, it is pointless to account for then. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191349 91177308-0d34-0410-b5e6-96231b3b80d8
* CriticalAntiDepBreaker is no longer needed for armv7 scheduling.Andrew Trick2013-09-253-5/+5
| | | | | | | | | | | | | | | | | This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191348 91177308-0d34-0410-b5e6-96231b3b80d8
* Move LTO support library to a component, allowing it to be testedPeter Collingbourne2013-09-242-0/+0
| | | | | | more reliably across platforms. Patch by Tom Roeder! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191343 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing check to SETCC optimization.Eli Friedman2013-09-241-0/+18
| | | | | | PR17338. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191337 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-dwarfdump support for gnu_pubtypesDavid Blaikie2013-09-241-3/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191329 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r191314. Yi Jiang2013-09-241-0/+27
| | | | | | | | Some supplemental information for r191314: We would like to make sure SLP Vectorizer will not try to vectorize tiny trees even with a negative threshold so we set the cost to INT_MAX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191327 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify that we don't optimize null return checks to the nothrow_t version of ↵Benjamin Kramer2013-09-241-0/+23
| | | | | | operator new. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191325 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the size and expr arguments of .fill directive optional.Roman Divacky2013-09-241-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191318 91177308-0d34-0410-b5e6-96231b3b80d8
* MemoryBuiltins: Reinstate optimizing (uninitialized) loads from operator new.Benjamin Kramer2013-09-241-3/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191315 91177308-0d34-0410-b5e6-96231b3b80d8
* MemoryBuiltins: Fix operator new bits.Benjamin Kramer2013-09-241-0/+20
| | | | | | We really don't want to optimize malloc return value checks away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191313 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach MemoryBuiltins and InstructionSimplify that operator new never returns ↵Benjamin Kramer2013-09-241-0/+20
| | | | | | | | | | | | NULL. This is safe per C++11 18.6.1.1p3: [operator new returns] a non-null pointer to suitably aligned storage (3.7.4), or else throw a bad_alloc exception. This requirement is binding on a replacement version of this function. Brings us a tiny bit closer to eliminating more vector push_backs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191310 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. ↵Daniel Sanders2013-09-241-0/+132
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191306 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal ↵Daniel Sanders2013-09-241-0/+262
| | | | | | IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191304 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-241-8/+51
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191302 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-242-12/+336
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching ↵Daniel Sanders2013-09-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Non-constant BUILD_VECTOR's should be expanded to ↵Daniel Sanders2013-09-241-0/+110
| | | | | | | | | | INSERT_VECTOR_ELT instead of memory operations. The resulting code is the same length, but doesnt cause memory traffic or latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191297 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. ↵Daniel Sanders2013-09-241-0/+30
| | | | | | | | | not intrinsics) This covers the case where fmax_a can be used to implement ISD::FABS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191296 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching andi, ori, nori, and xori from normal ↵Daniel Sanders2013-09-241-0/+240
| | | | | | IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191293 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching max, maxi, min, mini from normal IR ↵Daniel Sanders2013-09-243-4/+1096
| | | | | | (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191291 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. ↵Daniel Sanders2013-09-244-7/+413
| | | | | | | | | not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191290 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Handling of atomic load/store, atomic rmw, cmpxchg.Evgeniy Stepanov2013-09-242-4/+193
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191287 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching comparisons from normal IR (i.e. not ↵Daniel Sanders2013-09-242-0/+1159
| | | | | | | | | | intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191286 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching slli, srai, and srli from normal IR ↵Daniel Sanders2013-09-241-0/+168
| | | | | | (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191285 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/AArch64/neon-scalar-reduce-pairwise.ll: Use -mtriple here, ↵NAKAMURA Takumi2013-09-241-1/+1
| | | | | | or aach64-pecoff might be misassumed on win32 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191275 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-2429-259/+862
| | | | | | | | | | | | Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
* [stackprotector] Forgot to add in PR number to test case.Michael Gottesman2013-09-241-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191261 91177308-0d34-0410-b5e6-96231b3b80d8
* [stackprotector] Allow for copies from vreg -> vreg to be in a terminator ↵Michael Gottesman2013-09-241-0/+63
| | | | | | | | | | | sequence. Sometimes a copy from a vreg -> vreg sneaks into the middle of a terminator sequence. It is safe to slice this into the stack protector success bb. This fixes PR16979. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191260 91177308-0d34-0410-b5e6-96231b3b80d8
* Add namespaces to the list of items that we expose via pubnames.Eric Christopher2013-09-241-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191257 91177308-0d34-0410-b5e6-96231b3b80d8
* Regenerate testcase from source.Eric Christopher2013-09-241-64/+70
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191256 91177308-0d34-0410-b5e6-96231b3b80d8
* Make dwarfdump-type-units.test order-independentDavid Blaikie2013-09-241-19/+26
| | | | | | | The order in which the comdat type unit sections appear in the output is unspecified and may vary from machine to machine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191253 91177308-0d34-0410-b5e6-96231b3b80d8
* Selecting the address from a very long chain of GEPs can blow the stack.Bill Wendling2013-09-241-0/+25607
| | | | | | | | | | | The recursive nature of the address selection code can cause the stack to explode if there is a long chain of GEPs. Convert the recursive bit into a iterative method to avoid this. <rdar://problem/12445434> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191252 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more external types to the pubtypes table. Expand the asmEric Christopher2013-09-231-0/+3
| | | | | | checking patch until we get full dumping support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191239 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-dwarfdump/libDebugInfo support for type unitsDavid Blaikie2013-09-233-0/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191234 91177308-0d34-0410-b5e6-96231b3b80d8
* Make nomips16 mask not repeat if it ends with a '.'.Reed Kotler2013-09-231-0/+19
| | | | | | | | This mask is purely for debugging and testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191231 91177308-0d34-0410-b5e6-96231b3b80d8
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