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* Implement NEON domain switching for scalar <-> S-register vmovs on ARMTim Northover2012-08-171-32/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162094 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen2012-08-163-21/+35
| | | | | | | | | | It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162061 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach GVN to reason about edges dominating uses. This allows it to handle casesRafael Espindola2012-08-161-0/+60
| | | | | | | | | | | | | where some fact lake a=b dominates a use in a phi, but doesn't dominate the basic block itself. This feature could also be implemented by splitting critical edges, but at least with the current algorithm reasoning about the dominance directly is faster. The time for running "opt -O2" in the testcase in pr10584 is 1.003 times slower and on gcc as a single file it is 1.0007 times faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162023 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm-fast-isel] Add support for fastcc.Jush Lu2012-08-161-0/+66
| | | | | | | | | Without fastcc support, the caller just falls through to CallingConv::C for fastcc, but callee still uses fastcc, this inconsistency of calling convention is a problem, and fastcc support can fix it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162013 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r162008.Akira Hatanaka2012-08-161-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162009 91177308-0d34-0410-b5e6-96231b3b80d8
* Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen2012-08-152-1/+61
| | | | | | | | | | | | | | The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework test so that it reproduces the error without the horrible flag.Bill Wendling2012-08-151-8/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161989 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove invalid test. This test requires that dead basic blocks be keptBill Wendling2012-08-151-19/+0
| | | | | | | | | | | | | | | | | around. That's not how we do things. Besides, the commit message tells us that it is covered by the GCC test suite. ------------------------------------------------------------------------ r127497 | zwarich | 2011-03-11 13:51:56 -0800 (Fri, 11 Mar 2011) | 3 lines Fix the GCC test suite issue exposed by r127477, which was caused by stack protector insertion not working correctly with unreachable code. Since that revision was rolled out, this test doesn't actual fail before this fix. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161985 91177308-0d34-0410-b5e6-96231b3b80d8
* Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng2012-08-151-17/+49
| | | | | | unaligned access. rdar://12091029 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161962 91177308-0d34-0410-b5e6-96231b3b80d8
* fix infinite loop in instcombine with more than 4GB memcpyMichael Liao2012-08-151-0/+8
| | | | | | | | | | | | | | - memcpy size is wrongly truncated into 32-bit and treat 8GB memcpy is 0-sized memcpy - as 0-sized memcpy/memset is already removed before SimplifyMemTransfer and SimplifyMemSet in visitCallInst, replace 0 checking with assertions. - replace getZExtValue() with getLimitedValue() according to Eli Friedman git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161923 91177308-0d34-0410-b5e6-96231b3b80d8
* The names of VFP variants of half-to-float conversion instructions wereAnton Korobeynikov2012-08-141-3/+3
| | | | | | | | | reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161907 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR11334Michael Liao2012-08-141-0/+56
| | | | | | | | | | | | | | - FP_EXTEND only support extending from vectors with matching elements. This results in the scalarization of extending to v2f64 from v2f32, which will be legalized to v4f32 not matching with v2f64. - add X86-specific VFPEXT supproting extending from v4f32 to v2f64. - add BUILD_VECTOR lowering helper to recover back the original extending from v4f32 to v2f64. - test case is enhanced to include different vector width. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161894 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] insert crash basic blocks inline as opposed to inserting them at the ↵Kostya Serebryany2012-08-141-10/+8
| | | | | | end of the function. This doesn't seem to fix or break anything, but is considered to be more friendly to downstream passes (test change) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161871 91177308-0d34-0410-b5e6-96231b3b80d8
* Change greater than to greater than or equal so that an identical sized ↵Craig Topper2012-08-141-0/+19
| | | | | | store to the same offset is treated as completing overwriting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161857 91177308-0d34-0410-b5e6-96231b3b80d8
* During the CodeGenPrepare we often lower intrinsics (such as objsize)Nadav Rotem2012-08-147-22/+23
| | | | | | | | | | | | | and allow some optimizations to turn conditional branches into unconditional. This commit adds a simple control-flow optimization which merges two consecutive basic blocks which are connected by a single edge. This allows the codegen to operate on larger basic blocks. rdar://11973998 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161852 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/ARM/floorf.ll: Add explicit -mtriple=arm-unknown-unknown, ↵NAKAMURA Takumi2012-08-141-1/+1
| | | | | | or it fails on msvc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161825 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a roundToIntegral method to APFloat, which can be parameterized over ↵Owen Anderson2012-08-131-0/+29
| | | | | | various rounding modes. Use this to implement SelectionDAG constant folding of FFLOOR, FCEIL, and FTRUNC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161807 91177308-0d34-0410-b5e6-96231b3b80d8
* MemoryDependenceAnalysis attempts to find the first memory dependency for ↵Nadav Rotem2012-08-131-0/+34
| | | | | | | | | | | | | function calls. Currently, if GetLocation reports that it did not find a valid pointer (this is the case for volatile load/stores), we ignore the result. This patch adds code to handle the cases where we did not obtain a valid pointer. rdar://11872864 PR12899 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161802 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.Jim Grosbach2012-08-132-8/+10
| | | | | | These tests weren't actually being run before (missing ':' after CHECK). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161800 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename test since it's not linux-specific.Bill Wendling2012-08-131-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161792 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle extra Tail predecessors in if-conversion.Jakob Stoklund Olesen2012-08-131-0/+30
| | | | | | | | It is still possible to if-convert if the tail block has extra predecessors, but the tail phis must be rewritten instead of being removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161781 91177308-0d34-0410-b5e6-96231b3b80d8
* [Hexagon] Don't mark callee saved registers as clobbered by a tail callArnold Schwaighofer2012-08-131-0/+14
| | | | | | | | | | | | This was causing unnecessary spills/restores of callee saved registers. Fixes PR13572. Patch by Pranav Bhandarkar! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161778 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix failure on Atom bot due to r161769Manman Ren2012-08-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161777 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ↵Nadav Rotem2012-08-131-0/+17
| | | | | | | | | | ISDNode has more than one user. rdar://11876519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161775 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: move Int_CVTSD2SSrr, Int_CVTSI2SSrr, Int_CVTSI2SDrr, Int_CVTSS2SDrr fromManman Ren2012-08-131-0/+14
| | | | | | | | | | OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161769 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the %H output modifier.Eric Christopher2012-08-131-0/+9
| | | | | | Patch by Weiming Zhao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161768 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test for previous commit correcting NEON load patterns.Tim Northover2012-08-131-0/+102
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161750 91177308-0d34-0410-b5e6-96231b3b80d8
* Give this test an explicit triple.Nick Lewycky2012-08-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161740 91177308-0d34-0410-b5e6-96231b3b80d8
* When emitting the PC range in an FDE, use the same data encoding for both endsNick Lewycky2012-08-121-0/+28
| | | | | | | of the range. Fixes PR13581! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161739 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer2012-08-122-88/+0
| | | | | | | | | | architecture It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7 thumb O3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161736 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR13577, an issue introduced by r161687Michael Liao2012-08-111-0/+8
| | | | | | | | | | - FCMOV only supports a subset of X86 conditions. Skip boolean simplification if X86 condition is not valid for FCMOV. - add a minimal test case for PR13577. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161732 91177308-0d34-0410-b5e6-96231b3b80d8
* PR13578: Teach MachineCSE that instructions that use a constant register can ↵Benjamin Kramer2012-08-112-2/+24
| | | | | | | | be CSE'd safely. This is common e.g. when doing rip-relative addressing on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161728 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: when we are auto-detecting the subtarget features, make sure we turn onManman Ren2012-08-101-1/+3
| | | | | | | | | | | | FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge. FeatureFastUAMem is already on if we pass in nehalem or westmere as a command argument. rdar: 7252306 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161717 91177308-0d34-0410-b5e6-96231b3b80d8
* The normal edge of an invoke is not allowed to branch to a block with aEli Friedman2012-08-108-1204/+24
| | | | | | | | landingpad. Enforce it in the verifier, and fix the regression tests to match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161697 91177308-0d34-0410-b5e6-96231b3b80d8
* add X86-specific DAG optimization to simplify boolean testMichael Liao2012-08-101-0/+42
| | | | | | | | | | | | | | | - if a boolean test (X86ISD::CMP or X86ISD:SUB) checks a boolean value generated from X86ISD::SETCC, try to simplify the boolean value generation and checking by reusing the original EFLAGS with proper condition code - add hooks to X86 specific SETCC/BRCOND/CMOV, the major 3 places consuming EFLAGS part of patches fixing PR12312 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161687 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix crash when when do lto on Bullet. Dynamic GEPs in SROA were incorrectly ↵Pete Cooper2012-08-101-0/+22
| | | | | | being applied to all accesses to an alloca, not just the ones which read from the GEP. Thanks to Evan for reducing the test. rdar://11861001 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161654 91177308-0d34-0410-b5e6-96231b3b80d8
* Update edge weights correctly in replaceSuccessor().Jakob Stoklund Olesen2012-08-101-1/+1
| | | | | | | | When replacing Old with New, it can happen that New is already a successor. Add the old and new edge weights instead of creating a duplicate edge. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161653 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r161633-161634 "Partition use lists so defs always come before uses.""Jakob Stoklund Olesen2012-08-102-2/+2
| | | | | | | No changes to these patches, MRI needed to be notified when changing uses into defs and vice versa. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161644 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r161633-161634 "Partition use lists so defs always come before uses."Jakob Stoklund Olesen2012-08-092-2/+2
| | | | | | These commits broke a number of buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161640 91177308-0d34-0410-b5e6-96231b3b80d8
* Partition use lists so defs always come before uses.Jakob Stoklund Olesen2012-08-092-3/+3
| | | | | | | | | | | | | | | | This makes it possible to speed up def_iterator by stopping at the first use. This makes def_empty() and getUniqueVRegDef() much faster when there are many uses. In a +Asserts build, LiveVariables is 100x faster in one case because getVRegDef() has an assertion that would scan to the end of a def_iterator chain. Spill weight calculation is significantly faster (300x in one case) because isTriviallyReMaterializable() calls MRI->isConstantPhysReg(%RIP) which calls def_empty(%RIP). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161634 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use pointer-pointers for the register use lists.Jakob Stoklund Olesen2012-08-092-3/+3
| | | | | | | | | | | Use a more conventional doubly linked list where the Prev pointers form a cycle. This means it is no longer necessary to adjust the Prev pointers when reallocating the VRegInfo array. The test changes are required because the register allocation hint is using the use-list order to break ties. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161633 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't modify MO while use_iterator is still pointing to it.Jakob Stoklund Olesen2012-08-091-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161626 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the LLVM test makefile to run the extra Clang tools' test suitesChandler Carruth2012-08-091-0/+9
| | | | | | as part of check-all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161610 91177308-0d34-0410-b5e6-96231b3b80d8
* Another 32 to 64 bit sign extension bug.Jack Carter2012-08-091-4/+9
| | | | | | | The fields in the td definition were switched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161607 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-08-092-0/+88
| | | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161581 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the legalization of ExtLoad on ARM. ExpandUnalignedLoad did not properly Nadav Rotem2012-08-091-0/+12
| | | | | | | | | handle the cases where the memory value type was illegal. PR 13111. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161565 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test triples to fix win32 failures. Revert workaround from r161292.Bob Wilson2012-08-0810-22/+22
| | | | | | I don't have a win32 system to test, so hopefully I got them all fixed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161519 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/MC/COFF/seh.s: Fixup corresponding to r161487.NAKAMURA Takumi2012-08-081-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161489 91177308-0d34-0410-b5e6-96231b3b80d8
* Add `.pushsection', `.popsection', and `.previous' directives to Darwin ASM.Bill Wendling2012-08-082-0/+29
| | | | | | | | | | | | | | | | | | | | | There are situations where inline ASM may want to change the section -- for instance, to create a variable in the .data section. However, it cannot do this without (potentially) restoring to the wrong section. E.g.: asm volatile (".section __DATA, __data\n\t" ".globl _fnord\n\t" "_fnord: .quad 1f\n\t" ".text\n\t" "1:" :::); This may be wrong if this is inlined into a function that has a "section" attribute. The user should use `.pushsection' and `.popsection' here instead. The addition of `.previous' is added for completeness. <rdar://problem/12048387> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161477 91177308-0d34-0410-b5e6-96231b3b80d8
* isAllocLikeFn is allowed to return true for functions which read memory; makeEli Friedman2012-08-081-0/+15
| | | | | | | | | sure we account for that correctly in DeadStoreElimination. Fixes a regression from r158919. PR13547. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161468 91177308-0d34-0410-b5e6-96231b3b80d8
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