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* Re-enable the test with fix.Evan Cheng2010-07-141-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108319 91177308-0d34-0410-b5e6-96231b3b80d8
* temporarily disable to test to fix buildbots.Chris Lattner2010-07-141-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108310 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach ProcessImplicitDefs to transform more COPY instructions into ↵Evan Cheng2010-07-141-1/+1
| | | | | | IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108304 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.Bob Wilson2010-07-141-0/+12
| | | | | | | Radar 7373643. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256-bit compare instructions and a bunch of testcasesBruno Cardoso Lopes2010-07-132-0/+448
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108286 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to representBob Wilson2010-07-131-1/+1
| | | | | | | NEON VMOV-immediate instructions. This simplifies some things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX 256-bit conversion instructionsBruno Cardoso Lopes2010-07-132-0/+208
| | | | | | | Add the x86 VEX_L form to handle special cases where VEX_L must be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
* In inline asm treat indirect 'X' constraint as 'm'.Dale Johannesen2010-07-131-0/+18
| | | | | | | | | This may not be right in all cases, but it's better than asserting which it was doing before. PR 7528. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108268 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for empty named metadata too. This isn't particularlyDan Gohman2010-07-131-0/+1
| | | | | | | useful, but it is nice for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108262 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for empty metadata nodes: !{}.Dan Gohman2010-07-131-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108259 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend the r107852 optimization which turns some fp compare to code sequence ↵Evan Cheng2010-07-131-9/+62
| | | | | | using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
* -enable-unsafe-fp-math should not imply -enable-finite-only-fp-math.Evan Cheng2010-07-133-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108254 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR number.Dale Johannesen2010-07-131-1/+1
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* Handle the case of a tail recursion in which the tail call is followedDuncan Sands2010-07-131-1/+4
| | | | | | | | | | by a return that returns a constant, while elsewhere in the function another return instruction returns a different constant. This is a special case of accumulator recursion, so just generalize the existing logic a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108241 91177308-0d34-0410-b5e6-96231b3b80d8
* my work on adding segment registers to LEA missed the Chris Lattner2010-07-131-0/+3
| | | | | | | | disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256-bit packed logical formsBruno Cardoso Lopes2010-07-132-0/+128
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108224 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256-bit unop arithmetic instructionsBruno Cardoso Lopes2010-07-132-0/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108223 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256 binary arithmetic instructionsBruno Cardoso Lopes2010-07-122-0/+192
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108207 91177308-0d34-0410-b5e6-96231b3b80d8
* Apply the SSE dependence idiom for SSE unary operations toDan Gohman2010-07-121-0/+41
| | | | | | | | SD instructions too, in addition to SS instructions. And add a comment about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108191 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256-bit MOVMSK formsBruno Cardoso Lopes2010-07-122-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108184 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser.Daniel Dunbar2010-07-122-3/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108180 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/AsmParser: Move .desc parsing to Darwin specific parser.Daniel Dunbar2010-07-121-1/+1
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* MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser.Daniel Dunbar2010-07-122-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108174 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a lint check for mismatched return types, inspired by PR6944.Dan Gohman2010-07-121-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108162 91177308-0d34-0410-b5e6-96231b3b80d8
* Nope, still breaks the release selfhost bots :(Benjamin Kramer2010-07-121-13/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108153 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply the "or" half of r108136, which seems to be less problematic.Benjamin Kramer2010-07-121-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108152 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r108141 again, sigh.Benjamin Kramer2010-07-122-27/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108148 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply 108136 with an ugly pasto fixed.Benjamin Kramer2010-07-122-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108141 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r108136 until I figure out why it broke selfhost.Benjamin Kramer2010-07-122-28/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108139 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: fold (x & y) | (~x & z) and (x & y) ^ (~x & z) into ((y ^ z) & ↵Benjamin Kramer2010-07-122-0/+28
| | | | | | | | | | | | | | | | | | x) ^ z which is one instruction shorter. (PR6773) before: %and = and i32 %y, %x %neg = xor i32 %x, -1 %and4 = and i32 %z, %neg %xor = xor i32 %and4, %and after: %xor1 = xor i32 %z, %y %and2 = and i32 %xor1, %x %xor = xor i32 %and2, %z git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108136 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR7311 by avoiding breaking casts when a bitcast from scalar->vectorChris Lattner2010-07-121-0/+11
| | | | | | | is involved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108117 91177308-0d34-0410-b5e6-96231b3b80d8
* if jump threading is able to infer interesting values on bothChris Lattner2010-07-121-0/+24
| | | | | | | | | the LHS and RHS of an and/or instruction, don't multiply add known predecessor values. This fixes the crash on testcase from PR7498 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108114 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR7429, a crash turning a load from a string into a float.Chris Lattner2010-07-121-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108113 91177308-0d34-0410-b5e6-96231b3b80d8
* convert to filechecconvert to filecheckkChris Lattner2010-07-121-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108112 91177308-0d34-0410-b5e6-96231b3b80d8
* merge two tests.Chris Lattner2010-07-122-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108111 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove TargetInstrInfo::copyRegToReg entirely.Jakob Stoklund Olesen2010-07-112-4/+3
| | | | | | | Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no longer a default implementation forwarding to copyRegToReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola2010-07-111-1/+23
| | | | | | | | | | | | | | | correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix this test.Dan Gohman2010-07-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108059 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheckize inline asm FP stack testsJakob Stoklund Olesen2010-07-104-19/+89
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* Add an explicit triple to make this test behave consistently.Dan Gohman2010-07-101-1/+1
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* Fix this XTARGET so that this does doesn't XPASS on non-darwin hosts.Dan Gohman2010-07-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108040 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-103-9/+40
| | | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256-bit packed MOVNT variantsBruno Cardoso Lopes2010-07-092-0/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108021 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 256-bit unpack and interleaveBruno Cardoso Lopes2010-07-092-0/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108017 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few testsJakob Stoklund Olesen2010-07-091-60/+60
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108011 91177308-0d34-0410-b5e6-96231b3b80d8
* In the presence of variable sized objects, allocate an emergency spill slot.Jim Grosbach2010-07-091-2/+2
| | | | | | rdar://8131327 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a target triple.Dan Gohman2010-07-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108003 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix MachineLICM to actually visit inner loops.Dan Gohman2010-07-091-0/+89
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108001 91177308-0d34-0410-b5e6-96231b3b80d8
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-092-0/+98
| | | | | | | | | | | | | | | | | notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-092-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
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