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* NEON VST4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-17/+39
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-19/+39
* Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth2012-01-241-3/+2
* NEON VST3(single element from one lane) assembly parsing.Jim Grosbach2012-01-241-0/+35
* NEON VST3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-231-19/+39
* NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-232-65/+73
* Intel syntax: Robustify parsing of memory operand's displacement experssion.Devang Patel2012-01-231-2/+4
* NEON VLD3 lane-indexed assembly parsing and encoding.Jim Grosbach2012-01-231-11/+33
* Add support for .cfi_signal_frame. Fixes pr11762.Rafael Espindola2012-01-231-0/+23
* Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen2012-01-231-0/+105
* Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]Devang Patel2012-01-231-1/+3
* Simplify some NEON assembly pseudo definitions.Jim Grosbach2012-01-231-8/+8
* Intel syntax: Parse segment registers.Devang Patel2012-01-231-0/+2
* An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov2012-01-231-2/+3
* Make Value::isDereferenceablePointer() handle unreachable code blocks. (ThisNick Lewycky2012-01-231-0/+28
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-221-0/+68
* Intel syntax: Robustify register parsing.Devang Patel2012-01-201-0/+2
* Handle a corner case with IV chain collection with bailout instead of assert.Andrew Trick2012-01-201-0/+43
* Test case comments missing from my previous checkin.Andrew Trick2012-01-201-0/+5
* Intel syntax: Parse ... PTR [-8]Devang Patel2012-01-201-1/+2
* Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.Devang Patel2012-01-201-1/+4
* ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>Bob Wilson2012-01-201-0/+17
* VST2 four-register w/ update pseudos for fixed/register update.Jim Grosbach2012-01-201-0/+9
* NEON use vmov.i32 to splat some f32 values into vectors.Jim Grosbach2012-01-201-0/+8
* Fix CountCodeReductionForAlloca to more accurately represent what SROA can andNick Lewycky2012-01-201-0/+44
* SCEVExpander fixes. Affects LSR and indvars.Andrew Trick2012-01-201-0/+37
* Add support for selecting 256-bit PALIGNR.Craig Topper2012-01-201-0/+57
* Remove a low-quality test which was failing on Windows; test/CodeGen/X86/sret...Eli Friedman2012-01-201-23/+0
* Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.Eli Friedman2012-01-201-0/+28
* Set the "tail" flag on pattern-matched objc_storeStrong calls.Dan Gohman2012-01-192-2/+2
* Post process 'and', 'sub' instructions and select better encoding, if available.Devang Patel2012-01-191-0/+8
* Intel syntax: There is no need to create unary expr for simple negative displ...Devang Patel2012-01-191-0/+4
* Post process 'xor', 'or' and 'cmp' instructions and select better encoding, i...Devang Patel2012-01-191-0/+22
* Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov2012-01-191-0/+15
* Add testcase.Jim Grosbach2012-01-191-0/+13
* Space after punctuation.Nick Lewycky2012-01-191-14/+14
* Add a TargetOption for disabling tail calls.Nick Lewycky2012-01-191-0/+40
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-181-0/+27
* Process instructions after match to select alternative encoding which may be ...Devang Patel2012-01-181-0/+24
* Thumb2 relaxation for LDR(literal).Jim Grosbach2012-01-181-0/+13
* Use llvm.global_ctors to locate global constructors insteadDan Gohman2012-01-181-0/+2
* Fix a bug in the type-legalization of vector integers. When we bitcast one ve...Nadav Rotem2012-01-181-0/+14
* Test case renameAndrew Trick2012-01-171-0/+0
* MC tweak symbol difference resolution for non-local symbols.Jim Grosbach2012-01-173-5/+7
* Tidy up.Jim Grosbach2012-01-171-2/+2
* Intel syntax: Fix parser match class to check memory operand size.Devang Patel2012-01-171-0/+2
* Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem2012-01-173-5/+31
* Intel syntax: Parse "BYTE PTR [RDX + RCX]"Devang Patel2012-01-171-0/+2
* Add a new ObjC ARC optimization pass to eliminate unneededDan Gohman2012-01-171-0/+51
* Intel syntax: Do not unncessarily create plus expression for memory operand d...Devang Patel2012-01-171-0/+2