aboutsummaryrefslogtreecommitdiffstats
path: root/test
Commit message (Collapse)AuthorAgeFilesLines
* NEON VST4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-17/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-19/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth2012-01-241-3/+2
| | | | | | | | | | | | | | | | | | violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148759 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VST3(single element from one lane) assembly parsing.Jim Grosbach2012-01-241-0/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VST3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-231-19/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-232-65/+73
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Robustify parsing of memory operand's displacement experssion.Devang Patel2012-01-231-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON VLD3 lane-indexed assembly parsing and encoding.Jim Grosbach2012-01-231-11/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for .cfi_signal_frame. Fixes pr11762.Rafael Espindola2012-01-231-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148733 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR11829. PostRA LICM was too aggressive.Jakob Stoklund Olesen2012-01-231-0/+105
| | | | | | This fixes a typo in r148589. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148724 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]Devang Patel2012-01-231-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify some NEON assembly pseudo definitions.Jim Grosbach2012-01-231-8/+8
| | | | | | | Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Parse segment registers.Devang Patel2012-01-231-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
* An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov2012-01-231-2/+3
| | | | | | | | | This change adds an new value to the --arm-enable-ehabi option that disables emitting unwinding descriptors. This mode gives a working backtrace() without the (currently broken) exception support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148686 91177308-0d34-0410-b5e6-96231b3b80d8
* Make Value::isDereferenceablePointer() handle unreachable code blocks. (ThisNick Lewycky2012-01-231-0/+28
| | | | | | | | | returns false in the event the computation feeding into the pointer is unreachable, which maybe ought to be true -- but this is at least consistent with undef->isDereferenceablePointer().) Fixes PR11825! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148671 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-221-0/+68
| | | | | | | Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Robustify register parsing.Devang Patel2012-01-201-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle a corner case with IV chain collection with bailout instead of assert.Andrew Trick2012-01-201-0/+43
| | | | | | | Fixes PR11783: bad cast to AddRecExpr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148572 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case comments missing from my previous checkin.Andrew Trick2012-01-201-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148571 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Parse ... PTR [-8]Devang Patel2012-01-201-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148570 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.Devang Patel2012-01-201-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>Bob Wilson2012-01-201-0/+17
| | | | | | | | We have patterns for vector sext and zext operations but were missing anyext. Without those patterns, codegen will fail when the selection DAG has any_extend nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148568 91177308-0d34-0410-b5e6-96231b3b80d8
* VST2 four-register w/ update pseudos for fixed/register update.Jim Grosbach2012-01-201-0/+9
| | | | | | rdar://10724489 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148560 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON use vmov.i32 to splat some f32 values into vectors.Jim Grosbach2012-01-201-0/+8
| | | | | | | | | | | For bit patterns that aren't representable using the 8-bit floating point representation for vmov.f32, but are representable via vmov.i32, treat the .f32 syntax as an alias. Most importantly, this covers the case 'vmov.f32 Vd, #0.0'. rdar://10616677 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix CountCodeReductionForAlloca to more accurately represent what SROA can andNick Lewycky2012-01-201-0/+44
| | | | | | | | | can't handle. Also don't produce non-zero results for things which won't be transformed by SROA at all just because we saw the loads/stores before we saw the use of the address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148536 91177308-0d34-0410-b5e6-96231b3b80d8
* SCEVExpander fixes. Affects LSR and indvars.Andrew Trick2012-01-201-0/+37
| | | | | | | | | | | | | | | | | LSR has gradually been improved to more aggressively reuse existing code, particularly existing phi cycles. This exposed problems with the SCEVExpander's sloppy treatment of its insertion point. I applied some rigor to the insertion point problem that will hopefully avoid an endless bug cycle in this area. Changes: - Always used properlyDominates to check safe code hoisting. - The insertion point provided to SCEV is now considered a lower bound. This is usually a block terminator or the use itself. Under no cirumstance may SCEVExpander insert below this point. - LSR is reponsible for finding a "canonical" insertion point across expansion of different expressions. - Robust logic to determine whether IV increments are in "expanded" form and/or can be safely hoisted above some insertion point. Fixes PR11783: SCEVExpander assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148535 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for selecting 256-bit PALIGNR.Craig Topper2012-01-201-0/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a low-quality test which was failing on Windows; ↵Eli Friedman2012-01-201-23/+0
| | | | | | test/CodeGen/X86/sret.ll is a better test for the relevant behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148526 91177308-0d34-0410-b5e6-96231b3b80d8
* Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.Eli Friedman2012-01-201-0/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148513 91177308-0d34-0410-b5e6-96231b3b80d8
* Set the "tail" flag on pattern-matched objc_storeStrong calls.Dan Gohman2012-01-192-2/+2
| | | | | | | rdar://10531041. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148490 91177308-0d34-0410-b5e6-96231b3b80d8
* Post process 'and', 'sub' instructions and select better encoding, if available.Devang Patel2012-01-191-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: There is no need to create unary expr for simple negative ↵Devang Patel2012-01-191-0/+4
| | | | | | displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
* Post process 'xor', 'or' and 'cmp' instructions and select better encoding, ↵Devang Patel2012-01-191-0/+22
| | | | | | if available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov2012-01-191-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148473 91177308-0d34-0410-b5e6-96231b3b80d8
* Add testcase.Jim Grosbach2012-01-191-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148454 91177308-0d34-0410-b5e6-96231b3b80d8
* Space after punctuation.Nick Lewycky2012-01-191-14/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148451 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a TargetOption for disabling tail calls.Nick Lewycky2012-01-191-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-181-0/+27
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
* Process instructions after match to select alternative encoding which may be ↵Devang Patel2012-01-181-0/+24
| | | | | | more desirable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 relaxation for LDR(literal).Jim Grosbach2012-01-181-0/+13
| | | | | | | | | If the fixup is out of range for the Thumb1 instruction, relax it to the Thumb2 encoding instead. rdar://10711829 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148424 91177308-0d34-0410-b5e6-96231b3b80d8
* Use llvm.global_ctors to locate global constructors insteadDan Gohman2012-01-181-0/+2
| | | | | | | of recognizing them by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148416 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem2012-01-181-0/+14
| | | | | | vector type to another, we must not bitcast the result if one type is widened while the other is promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148383 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case renameAndrew Trick2012-01-171-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148344 91177308-0d34-0410-b5e6-96231b3b80d8
* MC tweak symbol difference resolution for non-local symbols.Jim Grosbach2012-01-173-5/+7
| | | | | | | | | | | | | | | | When the non-local symbol in the expression is in the same fragment as the second symbol, the assembler can still evaluate the expression without needing a relocation. For example, on ARM: _foo: ldr lr, (_foo - 4) rdar://10348687 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148341 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2012-01-171-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148339 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Fix parser match class to check memory operand size.Devang Patel2012-01-171-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
* Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem2012-01-173-5/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148337 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Parse "BYTE PTR [RDX + RCX]"Devang Patel2012-01-171-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new ObjC ARC optimization pass to eliminate unneededDan Gohman2012-01-171-0/+51
| | | | | | | autorelease push+pop pairs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148330 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Do not unncessarily create plus expression for memory operand ↵Devang Patel2012-01-171-0/+2
| | | | | | displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-01-13 07:27:47 +0000