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* X86: Fix encoding of 'movd %xmm0, %rax'Jim Grosbach2012-08-311-0/+4
* Take account of boolean vector contents when promoting a build vector from i1...Pete Cooper2012-08-301-0/+16
* Try to make this test more generic to unbreak buildbots.Owen Anderson2012-08-301-9/+9
* Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by co...Owen Anderson2012-08-301-0/+37
* [llvm] Updated the test fold-vector-select so that we test the vector selects...Michael Gottesman2012-08-301-9/+144
* Currently targets that do not support selects with scalar conditions and vect...Nadav Rotem2012-08-301-0/+17
* Introduce 'UseSSEx' to force SSE legacy encodingMichael Liao2012-08-302-5/+16
* Fix test case.Benjamin Kramer2012-08-301-1/+1
* LoopRotate: Also rotate loops with multiple exits.Benjamin Kramer2012-08-301-0/+200
* It is illegal to transform (sdiv (ashr X c1) c2) -> (sdiv x (2^c1 * c2)),Nadav Rotem2012-08-301-25/+0
* Add support for moving pure S-register to NEON pipeline if desiredTim Northover2012-08-301-0/+64
* Should put test case under test/ExecutionEngine/MCJIT/Michael Liao2012-08-301-0/+0
* Fix PR13727Michael Liao2012-08-301-0/+88
* Reserve space for the mandatory traceback fields on PPC64.Hal Finkel2012-08-291-0/+1
* Make MemoryBuiltins aware of TargetLibraryInfo.Benjamin Kramer2012-08-291-0/+31
* [arm-fast-isel] Add support for ARM PIC.Jush Lu2012-08-291-0/+43
* Create llvm/test/Object/Mips/lit.local.cfg to check Mips in targets_to_build.NAKAMURA Takumi2012-08-291-0/+5
* llvm/test: [CMake] Add profile_rt-shared to deps.NAKAMURA Takumi2012-08-291-0/+1
* llvm/test/Analysis/Profiling: Mark 3 of them as REQUIRES: loadable_module.NAKAMURA Takumi2012-08-293-0/+9
* Moved input for objdump test from Mips to Inputs.Jack Carter2012-08-292-1/+1
* Profile: set branch weight metadata with data generated from profiling.Manman Ren2012-08-283-0/+466
* The instruction DEXT may be transformed into DEXTU or DEXTM dependingJack Carter2012-08-281-0/+28
* Some of the instructions in the Mips instruction set are revisionJack Carter2012-08-282-0/+11
* Some instructions are passed to the assembler to beJack Carter2012-08-281-1/+4
* Emit word of zeroes after the last instruction as a start of the mandatoryRoman Divacky2012-08-281-0/+10
* Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel2012-08-282-0/+44
* InstCombine: Guard the transform introduced in r162743 against large ints and...Benjamin Kramer2012-08-281-2/+27
* Make sure that we don't call getZExtValue on values > 64 bits.Nadav Rotem2012-08-281-0/+7
* Teach InstCombine to canonicalize [SU]div+[AL]shl patterns.Nadav Rotem2012-08-282-2/+52
* The commutative flag is already correctly set within the multiclass. If we setBill Wendling2012-08-281-0/+20
* Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper2012-08-281-1/+1
* llvm/test/CodeGen/X86/pr12312.ll: Add -mtriple=x86_64-unknown-unknown.NAKAMURA Takumi2012-08-281-2/+2
* Fix PR12312Michael Liao2012-08-281-0/+48
* Remove extra MayLoad/MayStore flags from atomic_load/store.Jakob Stoklund Olesen2012-08-282-6/+0
* Fix mips' long branch pass.Akira Hatanaka2012-08-282-4/+13
* Fix bug 13532.Akira Hatanaka2012-08-281-0/+12
* Allow remat of LI on PPC.Hal Finkel2012-08-282-2/+18
* Eliminate redundant CR moves on PPC32.Hal Finkel2012-08-281-0/+26
* Optimize zext on PPC64.Hal Finkel2012-08-281-0/+11
* Make sure we add the predicate after all of the registers are added.Bill Wendling2012-08-271-0/+129
* llvm/test/CodeGen/X86/fma.ll: Add -march=x86, or two tests would fail on non-...NAKAMURA Takumi2012-08-271-2/+2
* llvm/test/CodeGen/X86/fma_patterns.ll: Add -mtriple=x86_64. It was incompatib...NAKAMURA Takumi2012-08-271-1/+1
* Commit test change for r162658.Craig Topper2012-08-271-44/+0
* Add basic support for .debug_ranges section to LLVM's DebugInfo library.Alexey Samsonov2012-08-271-0/+10
* FMA3 tests on bdver2 target for changes made in rev 162012. Also madeAnitha Boyapati2012-08-274-7/+12
* Make sure that FMA3 is favored even when FMA4 is also enabled. Test case for ...Craig Topper2012-08-271-1/+2
* Infer instruction properties from single-instruction patterns.Jakob Stoklund Olesen2012-08-242-0/+6
* Disable Mips' delay slot filler when optimization level is O0.Akira Hatanaka2012-08-241-6/+12
* In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if itsAkira Hatanaka2012-08-241-1/+1
* BranchProb: modify the definition of an edge in BranchProbabilityInfo to handleManman Ren2012-08-242-0/+59
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