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* Revert r192758 (and r192759), "MC: Better handling of tricky symbol and ↵NAKAMURA Takumi2013-10-164-24/+4
| | | | | | | | | | | | | | | section names" GNU AS didn't like quotes in symbol names. Error: junk at end of line, first unrecognized character is `"' .def "@feat.00"; "@feat.00" = 1 Reproduced on Cygwin's 2.23.52.20130309 and mingw32's 2.20.1.20100303. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192775 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a triple to this test.Rafael Espindola2013-10-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192767 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for metadata representing .ident directives.Rafael Espindola2013-10-164-0/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192764 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a pair of bugs in the emission of pubname tables:Eric Christopher2013-10-161-23/+46
| | | | | | | | | | | | | | | | 1) Make sure we emit static member variables by checking at the end of createGlobalVariableDIE rather than piecemeal in the function. (As a note, createGlobalVariableDIE needs rewriting.) 2) Make sure we use the definition rather than declaration DIE for two things: a) determining linkage for gnu pubnames, and b) as the address of the DIE for global variables. (As a note, createGlobalVariableDIE really needs rewriting.) Adjust the testcase to make sure we're checking the correct DIEs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192761 91177308-0d34-0410-b5e6-96231b3b80d8
* dos2unix on quoted-names.llHans Wennborg2013-10-161-20/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192759 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Better handling of tricky symbol and section namesHans Wennborg2013-10-164-4/+24
| | | | | | | | | | | | | | | | | Because of win32 mangling, we produce symbol and section names with funny characters in them, most notably @ characters. MC would choke on trying to parse its own assembly output. This patch addresses that by: - Making @ trigger quoting of symbol names - Also quote section names in the same way - Just parse section names like other identifiers (to allow for quotes) - Don't assume @ signifies a symbol variant if it is in a string. Differential Revision: http://llvm-reviews.chandlerc.com/D1945 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192758 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable MI Sched for x86.Andrew Trick2013-10-1566-279/+337
| | | | | | | | | | | | | | | | | | | | | | | | | | This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar signed saturating absolute value andChad Rosier2013-10-155-0/+156
| | | | | | scalar signed saturating negate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192733 91177308-0d34-0410-b5e6-96231b3b80d8
* Struct byval: fix a copy-paste error for thumb2.Manman Ren2013-10-151-4/+43
| | | | | | | PR17309 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192730 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR17546Michael Liao2013-10-151-0/+10
| | | | | | | | | | | | - Type of index used in extract_vector_elt or insert_vector_elt supposes to be TLI.getVectorIdxTy() which is pointer type on most targets. It'd better to truncate (or zero-extend in case it's changed later) it to mask element type to guarantee they are matching instead of asserting that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192722 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR16807Michael Liao2013-10-151-0/+18
| | | | | | | | | | | | - Lower signed division by constant powers-of-2 to target-independent DAG operators instead of target-dependent ones to support them better on targets where vector types are legal but shift operators on that types are illegal. E.g., on AVX, PSRAW is only available on <8 x i16> though <16 x i16> is a legal type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192721 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for build_vector for v4f32 and v2f64.Daniel Sanders2013-10-151-4/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192699 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use A(G)SI when spilling the target of a constant additionRichard Sandiford2013-10-152-0/+332
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192681 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix MSP430 calling convention to match MSPGCCJob Noorman2013-10-152-0/+179
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192678 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/break-avx-dep.ll: Relax an expression to be matched to ↵NAKAMURA Takumi2013-10-151-1/+1
| | | | | | also r[89], not only rXX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192675 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve on r192635, ExeDepsFix for avx, and add a test case.Andrew Trick2013-10-151-0/+29
| | | | | | | | | rdar:15221834 False AVX register dependencies cause 5x slowdown on flops-5/6 and significant slowdown on several others. This was blocking the switch to MI-Sched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192669 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Transfer kill flag to the newly created operand.Akira Hatanaka2013-10-152-6/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192662 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Set HI/LO registers' HWEncoding field.Akira Hatanaka2013-10-151-0/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192661 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86][FastISel] During X86 fastisel, the address of indirect call was resolvedQuentin Colombet2013-10-141-0/+132
| | | | | | | | | | | | | | | | through bitcast, ptrtoint, and inttoptr instructions. This is valid only if the related instructions are in that same basic block, otherwise we may reference variables that were not live accross basic blocks resulting in undefined virtual registers. The bug was exposed when both SDISel and FastISel were used within the same function, i.e., one basic block is issued with FastISel and another with SDISel, as demonstrated with the testcase. <rdar://problem/15192473> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192636 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo, in a comment, in a test.Nick Lewycky2013-10-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192632 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert part of a fix from 2010, changes since then:Eric Christopher2013-10-141-1/+5
| | | | | | | | | | | | a) x86-64 TLS has been documented b) the code path should use movq for the correct relocation to be generated. I've also added a fixme for the test case that we should improve the code generated, it should look something like is documented in the tls abi document. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192631 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineSink: Fix and tweak critical-edge breaking heuristic.Will Dietz2013-10-149-20/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per original comment, the intention of this loop is to go ahead and break the critical edge (in order to sink this instruction) if there's reason to believe doing so might "unblock" the sinking of additional instructions that define registers used by this one. The idea is that if we have a few instructions to sink "together" breaking the edge might be worthwhile. This commit makes a few small changes to help better realize this goal: First, modify the loop to ignore registers defined by this instruction. We don't sink definitions of physical registers, and sinking an SSA definition isn't going to unblock an upstream instruction. Second, ignore uses of physical registers. Instructions that define physical registers are rejected for sinking, and so moving this one won't enable moving any defining instructions. As an added bonus, while virtual register use-def chains are generally small due to SSA goodness, iteration over the uses and definitions (used by hasOneNonDBGUse) for physical registers like EFLAGS can be rather expensive in practice. (This is the original reason for looking at this) Finally, to keep things simple continue to only consider this trick for registers that have a single use (via hasOneNonDBGUse), but to avoid spuriously breaking critical edges only do so if the definition resides in the same MBB and therefore this one directly blocks it from being sunk as well. If sinking them together is meant to be, let the iterative nature of this pass sink the definition into this block first. Update tests to accomodate this change, add new testcase where sinking avoids pipeline stalls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192608 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Instrument x86.*_cvt* intrinsics.Evgeniy Stepanov2013-10-141-0/+66
| | | | | | | | | Currently MSan checks that arguments of *cvt* intrinsics are fully initialized. That's too much to ask: some of them only operate on lower half, or even quarter, of the input register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192599 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar integer compare instructions.Chad Rosier2013-10-144-0/+395
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Cortex-A57 supportBernard Ogden2013-10-141-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192591 91177308-0d34-0410-b5e6-96231b3b80d8
* Add subtarget feature support for Cortex-A53Bernard Ogden2013-10-143-6/+10
| | | | | | | Some previous implicit defaults have changed, for example FP and NEON are now on by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192590 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission support for BIT instructions.Matheus Almeida2013-10-141-0/+150
| | | | | | | | | | | | | | | | | | | | List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192589 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission support for VEC instructions.Matheus Almeida2013-10-141-0/+27
| | | | | | | | | List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192588 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.Matheus Almeida2013-10-141-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192587 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-141-0/+48
| | | | | | | | | | | | List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192586 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-141-0/+15
| | | | | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192582 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Fix handling of scalar select of vectors.Evgeniy Stepanov2013-10-141-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192575 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in dynamic allocation memory on stack.Elena Demikhovsky2013-10-143-3/+62
| | | | | | | | | The alignment of allocated space was wrong, see Bugzila 17345. Done by Zvi Rackover <zvi.rackover@intel.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192573 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-143-13/+13
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembler support for SSE4.1 register/register form of PEXTRW. There ↵Craig Topper2013-10-141-0/+6
| | | | | | is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the ↵Craig Topper2013-10-141-0/+8
| | | | | | disassembler tables. Add PINSRWrr64i to complement the AVX version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: improve dump of S_WAITCNTVincent Lejeune2013-10-131-0/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192557 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use masked read sel for texture instructionsVincent Lejeune2013-10-131-8/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192554 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: fix swizzle exportVincent Lejeune2013-10-132-1/+147
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192553 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: Sort PHINodes based on their opcodeArnold Schwaighofer2013-10-121-2/+34
| | | | | | | | | | | | | | Before this patch we relied on the order of phi nodes when we looked for phi nodes of the same type. This could prevent vectorization of cases where there was a phi node of a second type in between phi nodes of some type. This is important for vectorization of an internal graphics kernel. On the test suite + external on x86_64 (and on a run on armv7s) it showed no impact on either performance or compile time. radar://15024459 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192537 91177308-0d34-0410-b5e6-96231b3b80d8
* Force a CPU on test so it doesn't depend on microarchitectural scheduling ↵Benjamin Kramer2013-10-121-2/+2
| | | | | | decisions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192532 91177308-0d34-0410-b5e6-96231b3b80d8
* For Mips16, start to consolidate all forms of 32 bit literal loading so thatReed Kotler2013-10-121-6/+13
| | | | | | | | they can be better handled and optimized in the Mips16 constant island code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192520 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixing problems in lli's RemoteMemoryManager.Andrew Kaylor2013-10-112-2/+4
| | | | | | | | | | This fixes a problem from a previous check-in where a return value was omitted. Previously the remote/stubs-remote.ll and remote/stubs-sm-pic.ll tests were reporting passes, but they should have been failing. Those tests attempt to link against an external symbol and remote symbol resolution is not supported. The old RemoteMemoryManager implementation resulted in local symbols being used for resolution and the child process crashed but the test didn't notice. With this check-in remote symbol resolution fails, and so the test (correctly) fails. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192514 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding multiple object support to MCJIT EH frame handlingAndrew Kaylor2013-10-112-0/+65
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192504 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add scalar i32 add testMatt Arsenault2013-10-111-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192501 91177308-0d34-0410-b5e6-96231b3b80d8
* Use CHECK-LABELMatt Arsenault2013-10-111-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192500 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips: Disassemble sign-extended 64 bit immediates properly.Benjamin Kramer2013-10-111-0/+3
| | | | | | This doesn't change the meaning of the output, but makes look right. PR17539. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192483 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove kill flags after if conversion if necessaryMatthias Braun2013-10-111-0/+30
| | | | | | | | | | | | | | | | | | | When if converting something like: true: ... = R0<kill> false: ... = R0<kill> then the instructions of the true block must not have a <kill> flag anymore, as the instruction of the false block follow and do still read the R0 value. Specifically this patch determines the set of register live-in in the false block (possibly after simulating the liveness changes of the duplicated instructions). Each of these live-in registers mustn't be killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192482 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Load slicing test case: attempt to really fix the buildbots ↵Quentin Colombet2013-10-111-2/+2
| | | | | | | | | (used sse4.2 instead of avx!). <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192480 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info Testing Case: check for the name of a structure.Manman Ren2013-10-111-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192478 91177308-0d34-0410-b5e6-96231b3b80d8
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