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* [mips] brcond + setgt/setugt instruction selection patterns.Akira Hatanaka2013-06-051-0/+134
* [PATCH] Fix VGATHER* operand constraintsMichael Liao2013-06-051-0/+18
* This is a simple patch that changes RRX and RRXS to accept all registers as o...Mihai Popa2013-06-052-0/+47
* PR15662: Optimized debug info produces out of order function parametersDavid Blaikie2013-06-051-0/+73
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-051-0/+32
* Don't print default values for NumberOfAuxSymbols and AuxiliaryData.Rafael Espindola2013-06-051-0/+1
* Revert "R600: Add a pass that merge Vector Register"Rafael Espindola2013-06-051-30/+0
* Handle relocations that don't point to symbols.Rafael Espindola2013-06-052-0/+7
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-041-0/+30
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-041-0/+27
* Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2013-06-042-20/+23
* IndVarSimplify: check if loop invariant expansion can trapDavid Majnemer2013-06-041-0/+32
* ARM: Fix crash in ARM backend inside of ARMConstantIslandPassDavid Majnemer2013-06-041-0/+14
* R600: Swizzle texture/export instructionsVincent Lejeune2013-06-041-5/+5
* R600: Add a test for r183108Vincent Lejeune2013-06-041-0/+2
* Second part of pr16069Rafael Espindola2013-06-041-1/+15
* [llvm-symbolizer] Avoid calling slow getSymbolSize for Mach-O files. Assume t...Alexey Samsonov2013-06-041-0/+5
* SimplifyCFG: Do not transform PHI to select if doing so would be unsafeDavid Majnemer2013-06-031-0/+14
* Enable mcjit tests on ppc64 when building with cmake.Rafael Espindola2013-06-031-1/+3
* R600/SI: Add support for work item and work group intrinsicsTom Stellard2013-06-031-0/+211
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-037-10/+10
* R600/SI: Custom lower i64 sign_extendTom Stellard2013-06-031-0/+12
* R600/SI: Add support for global loadsTom Stellard2013-06-031-3/+49
* R600: use capital letter for PV channelVincent Lejeune2013-06-0314-17/+17
* Correct handling invalid filename in llvm-symbolizerAlexey Samsonov2013-06-031-0/+3
* Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju2013-06-031-0/+77
* [Object/COFF] Fix Windows .lib name handling.Rui Ueyama2013-06-033-0/+26
* Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2013-06-032-0/+27
* Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju2013-06-024-8/+125
* Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju2013-06-029-34/+36
* When determining the new index for an insertelement, we may not assume that anNick Lewycky2013-06-011-0/+11
* Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ...Venkatraman Govindaraju2013-06-012-0/+24
* Disable new legacy JIT test on ARM.Tim Northover2013-06-011-0/+1
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-011-4/+3
* TMP: LEA64_32r fixingTim Northover2013-06-011-3/+4
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-06-012-10/+27
* [Sparc] Generate correct code for leaf functions with stack objects Venkatraman Govindaraju2013-06-011-0/+23
* Prevent loop-unroll from making assumptions about undefined behavior.Andrew Trick2013-05-312-22/+62
* Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher2013-05-311-10/+10
* LoopVectorize: PHIs with only outside users should prevent vectorizationArnold Schwaighofer2013-05-311-0/+41
* Modify how the formulae are rated in Loop Strength Reduce.Quentin Colombet2013-05-313-9/+64
* Unit test for SCEV fix r182989, PR16130.Andrew Trick2013-05-311-3/+28
* ARM: permit upper-case BE/LE on setend instructionTim Northover2013-05-311-0/+4
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-313-0/+36
* Simplify multiplications by vectors whose elements are powers of 2.Rafael Espindola2013-05-311-0/+408
* ARM: fix VEXT encoding corner caseTim Northover2013-05-311-0/+5
* [SystemZ] Don't use LOAD and STORE REVERSED for volatile accessesRichard Sandiford2013-05-314-24/+72
* [NVPTX] Re-enable support for virtual registers in the final outputJustin Holewinski2013-05-312-35/+35
* [msan] Handle mixed track-origins and keep-going settings (llvm part).Evgeniy Stepanov2013-05-311-2/+3
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-311-10/+10
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