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* Temporarily revert "Debug Info Finder|Verifier: handle DbgLoc attached toEric Christopher2013-08-0214-36/+28
* fix for LLVM debug info on llvm-mips-linux where the label name uses % instea...Carlo Kok2013-08-011-1/+1
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-016-28/+705
* Fix some issues with Mips16 floating when certain intrinsics are present.Reed Kotler2013-08-011-0/+368
* ARM/Hexagon testcases can't compile x86 only testcase. Reverting change to te...Carlo Kok2013-08-011-2/+2
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-0114-28/+36
* DebugInfo: Emit definitions for types with no members.David Blaikie2013-08-011-15/+33
* change the inlinefnlocalvar testcase so it uses a triple that's not coff (doe...Carlo Kok2013-08-011-1/+1
* Temporarily xfail a test that breaks on OS X when building with LTO.Bob Wilson2013-08-011-0/+1
* Bugfix for making the DWARF debug strings and labels to code emitted as secre...Carlo Kok2013-08-011-0/+40
* R600: Add 64-bit float load/store supportTom Stellard2013-08-0115-43/+161
* R600: Use 64-bit alignment for 64-bit kernel argumentsTom Stellard2013-08-011-0/+2
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-011-0/+18
* EVEX and compressed displacement encoding for AVX512Elena Demikhovsky2013-08-011-0/+21
* [SystemZ] Reuse CC results for integer comparisons with zeroRichard Sandiford2013-08-012-0/+691
* [SystemZ] Prefer comparisons with zeroRichard Sandiford2013-08-015-10/+54
* Add tests for Mips DSP instructions.Vladimir Medic2013-08-011-0/+44
* AArch64: add initial NEON supportTim Northover2013-08-0147-6/+9812
* XCore target: Fix Vararg handlingRobert Lytton2013-08-012-17/+55
* XCore target: Add byval handlingRobert Lytton2013-08-011-0/+58
* Xcore targetRobert Lytton2013-08-011-0/+4
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-011-48/+50
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-312-0/+6
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-3125-185/+73
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-311-0/+68
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-3125-73/+185
* Reject bitcasts between address spaces with different sizesMatt Arsenault2013-07-319-0/+97
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-311-0/+25
* [SystemZ] Be more careful about inverting CC masks (conditional loads)Richard Sandiford2013-07-312-14/+14
* [SystemZ] Be more careful about inverting CC masksRichard Sandiford2013-07-3147-124/+149
* [SystemZ] Move compare-and-branch generation even laterRichard Sandiford2013-07-311-0/+45
* [SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()Richard Sandiford2013-07-3129-431/+446
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-311-0/+44
* [SystemZ] Add RISBLG and RISBHG instruction definitionsRichard Sandiford2013-07-314-0/+124
* Changed register names (and pointer keywords) to be lower case when using Int...Craig Topper2013-07-317-44/+44
* Preserve fast-math flags when folding (fsub x, (fneg y)) to (fadd x, y).Owen Anderson2013-07-301-0/+11
* isKnownToBeAPowerOfTwo: Strengthen isKnownToBeAPowerOfTwo's analysis on add i...David Majnemer2013-07-301-0/+32
* Change behavior of calling bitcasted alias functions.Matt Arsenault2013-07-306-59/+295
* This test may have been sensitive to the ARM ABI...Andrew Trick2013-07-301-1/+1
* MI Sched fix: assert "Disconnected LRG within the scheduling region."Andrew Trick2013-07-301-1/+54
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-304-36/+36
* This patch implements parsing of mips FCC register operands. The example inst...Vladimir Medic2013-07-301-0/+6
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-301-0/+32
* [R600] Replicate old DAGCombiner behavior in target specific DAG combine.Quentin Colombet2013-07-301-1/+0
* [DAGCombiner] insert_vector_elt: Avoid building a vector twice.Quentin Colombet2013-07-307-26/+53
* Move file to X86 and add a triple to fix darwin bots for now.Eric Christopher2013-07-301-1/+1
* Fix a truly egregious thinko in anonymous namespace check,Eric Christopher2013-07-291-66/+125
* Make sure we don't emit an ODR hash for types with no name and makeEric Christopher2013-07-291-19/+60
* Clarify comments for types contained in anonymous namespaces andEric Christopher2013-07-291-1/+3
* Debug Info: enable verifier for testing cases.Manman Ren2013-07-2910-11/+11
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