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* 'svn add' the test cases.Joey Gouly2013-09-185-0/+92
* Lift alignment restrictions for load/store folding on VINSERTF128/VEXTRACTF12...Craig Topper2013-09-181-2/+0
* Fix a constant folding address space place I missed.Matt Arsenault2013-09-171-0/+8
* COFF: Ensure that objects produced by LLVM link with /safesehReid Kleckner2013-09-172-0/+20
* Revert the load slicing done in r190870.Quentin Colombet2013-09-171-330/+0
* COFF: Emit all MCSymbols rather than filtering out some of themReid Kleckner2013-09-171-1/+10
* Cleanup handling of constant function casts.Matt Arsenault2013-09-171-1/+142
* [PowerPC] Fix problems with large code model (PR17169).Bill Schmidt2013-09-173-8/+12
* Costmodel: Add support for horizontal vector reductionsArnold Schwaighofer2013-09-171-0/+94
* SLPVectorizer: Don't vectorize phi nodes that use invoke valuesArnold Schwaighofer2013-09-171-0/+62
* [InstCombiner] Slice a big load in two loads when the elements are next to eachQuentin Colombet2013-09-171-0/+330
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-171-3/+13
* Bugfix for PR17099:Stepan Dyatkovskiy2013-09-171-0/+18
* Implement 3 AArch64 neon instructions : umov smov ins.Kevin Qin2013-09-172-0/+303
* [SelectionDAG] Teach the vector scalarizer about TRUNCATE.Quentin Colombet2013-09-171-0/+20
* mention command line parametersAdrian Prantl2013-09-171-0/+1
* Be sure we run ARM tests only when an ARM backend is present.Adrian Prantl2013-09-161-0/+4
* Debug info: Fix PR16736 and rdar://problem/14990587.Adrian Prantl2013-09-161-0/+63
* Add Atom Silvermont (slm) testsPreston Gurd2013-09-163-0/+23
* Add testcase for r190631Krzysztof Parzyszek2013-09-161-0/+54
* Don't vectorize if there are outside loop users of the induction variable.Arnold Schwaighofer2013-09-161-0/+30
* [msan] Check return value of main().Evgeniy Stepanov2013-09-161-0/+18
* This patch implements Mips load/store instructions from/to coprocessor 2. Tes...Vladimir Medic2013-09-161-0/+8
* [SystemZ] Improve extload handlingRichard Sandiford2013-09-161-2/+2
* Implement function prefix data as an IR feature.Peter Collingbourne2013-09-163-0/+42
* PPC: Don't restrict lvsl generation to after type legalizationHal Finkel2013-09-151-0/+166
* ELF: Add support for the exclude section bit for gas compat.Benjamin Kramer2013-09-151-4/+21
* MC: Add support for '?' flags in .section directivesDavid Majnemer2013-09-151-1/+1
* Fix alignment of unwind data.Kai Nacke2013-09-153-0/+226
* Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEHKai Nacke2013-09-152-11/+32
* Revert r190764: PPC: Don't restrict lvsl generation to after type legalizationHal Finkel2013-09-151-154/+0
* PPC: Don't restrict lvsl generation to after type legalizationHal Finkel2013-09-151-0/+154
* Prevent assert in CombinerGlobalAA with null valuesHal Finkel2013-09-151-0/+137
* Expand the mask capability for deciding which functions are mips16 and mips32Reed Kotler2013-09-151-0/+73
* Add the remaining Intel SHA instructionsBen Langmuir2013-09-142-1/+89
* Remove the long, long defunct IR block placement pass.Chandler Carruth2013-09-141-15/+0
* Fixed bug when generating Load Upper Immediate microMIPS instruction.Zoran Jovanovic2013-09-143-0/+9
* Support for microMIPS DIV instructions.Zoran Jovanovic2013-09-143-0/+18
* Support for misc microMIPS instructions.Zoran Jovanovic2013-09-142-0/+42
* Add missing CHECK-LABELMatt Arsenault2013-09-141-0/+1
* Add test for untested path in SimplifyCFGMatt Arsenault2013-09-141-6/+28
* Fix tests for hasFPARMv8 name change (r190692)Amaury de la Vieuville2013-09-135-5/+5
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-134-25/+25
* [ARMv8] Emit the proper .fpu directive.Joey Gouly2013-09-131-0/+7
* Add "native" to config.available_features, to make it easier to disable non-x...Amaury de la Vieuville2013-09-133-1/+13
* [SystemZ] Try to fold shifts into TMxxRichard Sandiford2013-09-132-0/+80
* AArch64: use RegisterOperand for NEON registers.Tim Northover2013-09-132-6/+11
* Add initial support for handling gnu style pubnames accepted by someEric Christopher2013-09-131-0/+126
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-121-0/+16
* R600: Move fabs/fneg/sel folding logic into PostProcessIselVincent Lejeune2013-09-121-0/+18
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