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* R600/SI: Add missing test for r187749Tom Stellard2013-08-051-0/+48
* LLVM Interpreter: This patch implements vector support for cast operations (z...Elena Demikhovsky2013-08-052-0/+178
* [SystemZ] Use BRCT and BRCTG to eliminate add-&-compare sequencesRichard Sandiford2013-08-053-1/+237
* [SystemZ] Add definitions for BRCT and BRCTGRichard Sandiford2013-08-053-0/+92
* [SystemZ] Use LOAD AND TEST to eliminate comparisons against zeroRichard Sandiford2013-08-051-0/+223
* [SystemZ] Add LOAD AND TEST instructionsRichard Sandiford2013-08-053-0/+246
* AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.Elena Demikhovsky2013-08-051-0/+58
* Add the saving of S2. This is needed for some of the floating pointReed Kotler2013-08-045-16/+17
* Remove "lto_on_osx" xfails, now that -rdynamic works on Darwin.Bob Wilson2013-08-045-8/+0
* X86: Turn fp selects into mask operations.Benjamin Kramer2013-08-043-48/+290
* AVX-512 set: added VEXTRACTPS instructionElena Demikhovsky2013-08-041-1/+20
* X86: specify CPU on new test to fix atom buildbotTim Northover2013-08-041-1/+1
* X86: correct tail return address calculationTim Northover2013-08-041-0/+19
* Clean up code for Mips16 large frame handling.Reed Kotler2013-08-041-12/+25
* Fix PPC64 64-bit GPR inline asm constraint matchingHal Finkel2013-08-031-0/+65
* [mips] Expand vector truncating stores and extending loads.Akira Hatanaka2013-08-021-0/+11
* [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.Joey Gouly2013-08-021-0/+3
* SLPVectorizer: Fix PR16777. PHInodes may use multiple extracted values that c...Nadav Rotem2013-08-021-0/+35
* Fixes ARM LNT bot from SLP change in O3Renato Golin2013-08-021-0/+8
* Bugfix for making the DWARF debug strings and labels to code emitted as secre...Carlo Kok2013-08-021-0/+40
* Fix handling of CHECK-DAG combined with CHECK-NOTTim Northover2013-08-021-0/+1
* Revert r187597, "Bugfix for making the DWARF debug strings and labels to code...NAKAMURA Takumi2013-08-021-40/+0
* Temporarily revert "Debug Info Finder|Verifier: handle DbgLoc attached toEric Christopher2013-08-0214-36/+28
* fix for LLVM debug info on llvm-mips-linux where the label name uses % instea...Carlo Kok2013-08-011-1/+1
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-016-28/+705
* Fix some issues with Mips16 floating when certain intrinsics are present.Reed Kotler2013-08-011-0/+368
* ARM/Hexagon testcases can't compile x86 only testcase. Reverting change to te...Carlo Kok2013-08-011-2/+2
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-0114-28/+36
* DebugInfo: Emit definitions for types with no members.David Blaikie2013-08-011-15/+33
* change the inlinefnlocalvar testcase so it uses a triple that's not coff (doe...Carlo Kok2013-08-011-1/+1
* Temporarily xfail a test that breaks on OS X when building with LTO.Bob Wilson2013-08-011-0/+1
* Bugfix for making the DWARF debug strings and labels to code emitted as secre...Carlo Kok2013-08-011-0/+40
* R600: Add 64-bit float load/store supportTom Stellard2013-08-0115-43/+161
* R600: Use 64-bit alignment for 64-bit kernel argumentsTom Stellard2013-08-011-0/+2
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-011-0/+18
* EVEX and compressed displacement encoding for AVX512Elena Demikhovsky2013-08-011-0/+21
* [SystemZ] Reuse CC results for integer comparisons with zeroRichard Sandiford2013-08-012-0/+691
* [SystemZ] Prefer comparisons with zeroRichard Sandiford2013-08-015-10/+54
* Add tests for Mips DSP instructions.Vladimir Medic2013-08-011-0/+44
* AArch64: add initial NEON supportTim Northover2013-08-0147-6/+9812
* XCore target: Fix Vararg handlingRobert Lytton2013-08-012-17/+55
* XCore target: Add byval handlingRobert Lytton2013-08-011-0/+58
* Xcore targetRobert Lytton2013-08-011-0/+4
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-011-48/+50
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-312-0/+6
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-3125-185/+73
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-311-0/+68
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-3125-73/+185
* Reject bitcasts between address spaces with different sizesMatt Arsenault2013-07-319-0/+97
* [SystemZ] Implement isLegalAddressingMode()Richard Sandiford2013-07-311-0/+25
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