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* X86: Fold EXTRACT_SUBVECTORs of a BUILD_VECTOR into a smaller BUILD_VECTOR.Benjamin Kramer2013-03-073-3/+18
| | | | | | | | | | That can usually be lowered efficiently and is common in sandybridge code. It would be nice to do this in DAGCombiner but we can't insert arbitrary BUILD_VECTORs this late. Fixes PR15462. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176634 91177308-0d34-0410-b5e6-96231b3b80d8
* SDAG: Handle scalarizing an extend of a <1 x iN> vector.Jim Grosbach2013-03-071-0/+19
| | | | | | | | | Just scalarize the element and rebuild a vector of the result type from that. rdar://13281568 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176614 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: store the files and directories for each compile unit.Manman Ren2013-03-071-3/+6
| | | | | | | | | | | | | | | We now emit a line table for each compile unit. To reduce the prologue size of each line table, the files and directories used by each compile unit are stored in std::map<unsigned, std::vector< > > instead of std::vector< >. The prologue for a lto'ed image can be as big as 93K. Duplicating 93K for each compile unit causes a huge increase of debug info. With this patch, each prologue will only emit the files required by the compile unit. rdar://problem/13342023 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176605 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG fix for volatile load/store.Andrew Trick2013-03-071-0/+48
| | | | | | | | | | | | | Fixes rdar:13349374. Volatile loads and stores need to be preserved even if the language standard says they are undefined. "volatile" in this context means "get out of the way compiler, let my platform handle it". Additionally, this is the only way I know of with llvm to write to the first page (when hardware allows) without dropping to assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176599 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two remaining issue after fixing PR15355 when CMOV is not availableMichael Liao2013-03-072-0/+67
| | | | | | | | | | | | | - Phi nodes should be replaced/updated after lowering CMOV into branch because 'mainMBB' updating operand in Phi node is changed. - Add EFLAGS in livein before lowering the 2nd CMOV. It's necessary as we will reuse the EFLAGS generated before the 1st lowered CMOV, which won't clobber EFLAGS. However, we need explicitly specify that. - '-attr=-cmov' test case are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176598 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Custom-legalize BR_JT.Akira Hatanaka2013-03-061-15/+20
| | | | | | | | In N64-static, GOT address is needed to compute the branch address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176580 91177308-0d34-0410-b5e6-96231b3b80d8
* Memory Dependence Analysis (not mem-dep test) take advantage of ↵Shuxin Yang2013-03-061-0/+29
| | | | | | | | | | | | | | | | | "invariant.load" metadata. The "invariant.load" metadata indicates the memory unit being accessed is immutable. A load annotated with this metadata can be moved across any store. As I am not sure if it is legal to move such loads across barrier/fence, this change dose not allow such transformation. rdar://11311484 Thank Arnold for code review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176562 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Don't shrink allocas when combining with a bitcast.Jim Grosbach2013-03-062-1/+46
| | | | | | | | | | When considering folding a bitcast of an alloca into the alloca itself, make sure we don't shrink the amount of memory being allocated, or things rapidly go sideways. rdar://13324424 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176547 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add a line which checks function name. Rename file.Akira Hatanaka2013-03-061-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176543 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR15355Michael Liao2013-03-0613-17/+17
| | | | | | | | | | | | | | | - Clear 'mayStore' flag when loading from the atomic variable before the spin loop - Clear kill flag from one use to multiple use in registers forming the address to that atomic variable - don't use a physical register as live-in register in BB (neither entry nor landing pad.) by copying it into virtual register (patch by Cameron Zwarich) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176538 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove android calling convention.Akira Hatanaka2013-03-051-12/+0
| | | | | | | | | This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176530 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 getsAkira Hatanaka2013-03-051-5/+5
| | | | | | | | returned in registers $2 and $4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176527 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctlyAkira Hatanaka2013-03-051-0/+18
| | | | | | | | handle fp128 returns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176523 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floatingAkira Hatanaka2013-03-051-0/+13
| | | | | | | | point registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176521 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Correct handling of fp128 (long double) formals and read long doubleAkira Hatanaka2013-03-051-0/+13
| | | | | | | | parameters from floating point registers if target is mips64 hard float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176520 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting patch 176508.Jyotsna Verma2013-03-052-78/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add support for lowering block address.Jyotsna Verma2013-03-052-0/+78
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Expand addc, adde, subc and sube.Jyotsna Verma2013-03-052-0/+63
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes a test by replacing .align by .p2align and setting triples explicitly.Eli Bendersky2013-03-051-2/+5
| | | | | | | | Patch by David Sehr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176502 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add encoding bits to the TFR64 instructions.Jyotsna Verma2013-03-052-5/+5
| | | | | | | | Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test that .align directives on capable processors use long NOPs.David Sehr2013-03-051-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176490 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Turn BUILD_VECTOR into Reg_SequenceVincent Lejeune2013-03-051-3/+3
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176487 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use MUL_IEEE for trig/fdiv intrinsicVincent Lejeune2013-03-051-4/+4
| | | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176485 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/Mips/mips64-f128.ll: Add explicit ↵NAKAMURA Takumi2013-03-051-1/+1
| | | | | | | | -mtriple=mips64el-unknown-unknown to appease win32. FIXME: Is it expected for win32 to affect mips targets? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176471 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown ↵NAKAMURA Takumi2013-03-051-1/+1
| | | | | | to appease win32 hosts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176470 91177308-0d34-0410-b5e6-96231b3b80d8
* The current X86 NOP padding uses one long NOP followed by the remainder inDavid Sehr2013-03-051-0/+27
| | | | | | | | | | | | one-byte NOPs. If the processor actually executes those NOPs, as it sometimes does with aligned bundling, this can have a performance impact. From my micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve one-byte NOPs is about 20% worse than a 15 followed by a 12. This patch changes NOP emission to emit as many 15-byte (the maximum) as possible followed by at most one shorter NOP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8
* Check isDiscardableIfUnused, rather than hasLocalLinkage, when bumpingLang Hames2013-03-041-0/+23
| | | | | | | | GlobalValue linkage up to ExternalLinkage in the ExtractGV pass. This prevents linkonce and linkonce_odr symbols from being DCE'd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176459 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Print move instructions.Akira Hatanaka2013-03-049-42/+42
| | | | | | | | "move $4, $5" is printed instead of "or $4, $5, $zero". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176455 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific inline assembler constraint 'R'Jack Carter2013-03-041-0/+9
| | | | | | | | | 'R' An address that can be sued in a non-macro load or store. This patch includes a positive test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176452 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r176381, writing the CHECKs in a more forgiving manner to account forEli Bendersky2013-03-041-14/+12
| | | | | | | running llvm-objdump on Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176443 91177308-0d34-0410-b5e6-96231b3b80d8
* Bypass Slow DividesPreston Gurd2013-03-042-1/+47
| | | | | | | | | | | | | | | | * Only apply divide bypass optimization when not optimizing for size. * Fixed bug caused by constant for 0 value of type Int32, used dividend type to generate the constant instead. * For atom x86-64 apply the divide bypass to use 16-bit divides instead of 64-bit divides when operand values are small enough. * Added lit tests for 64-bit divide bypass. Patch by Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176442 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Creating a vector from a lane of another.Jim Grosbach2013-03-021-0/+14
| | | | | | | | | | | The VDUP instruction source register doesn't allow a non-constant lane index, so make sure we don't construct a ARM::VDUPLANE node asking it to do so. rdar://13328063 http://llvm.org/bugs/show_bug.cgi?id=13963 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176413 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON: Fix v2f32 float intrinsicsArnold Schwaighofer2013-03-021-0/+377
| | | | | | Mark them as expand, they are not legal as our backend does not match them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176410 91177308-0d34-0410-b5e6-96231b3b80d8
* recommit r172363 & r171325 (reverted in r172756)Nuno Lopes2013-03-021-0/+128
| | | | | | | | This adds minimalistic support for PHI nodes to llvm.objectsize() evaluation fingers crossed so that it does break clang boostrap again.. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176408 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 cost model: Adjust cost for custom lowered vector multipliesArnold Schwaighofer2013-03-022-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matters for example in following matrix multiply: int **mmult(int rows, int cols, int **m1, int **m2, int **m3) { int i, j, k, val; for (i=0; i<rows; i++) { for (j=0; j<cols; j++) { val = 0; for (k=0; k<cols; k++) { val += m1[i][k] * m2[k][j]; } m3[i][j] = val; } } return(m3); } Taken from the test-suite benchmark Shootout. We estimate the cost of the multiply to be 2 while we generate 9 instructions for it and end up being quite a bit slower than the scalar version (48% on my machine). Also, properly differentiate between avx1 and avx2. On avx-1 we still split the vector into 2 128bits and handle the subvector muls like above with 9 instructions. Only on avx-2 will we have a cost of 9 for v4i64. I changed the test case in test/Transforms/LoopVectorize/X86/avx1.ll to use an add instead of a mul because with a mul we now no longer vectorize. I did verify that the mul would be indeed more expensive when vectorized with 3 kernels: for (i ...) r += a[i] * 3; for (i ...) m1[i] = m1[i] * 3; // This matches the test case in avx1.ll and a matrix multiply. In each case the vectorized version was considerably slower. radar://13304919 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176403 91177308-0d34-0410-b5e6-96231b3b80d8
* PR14448 - prevent the loop vectorizer from vectorizing the same loop twice.Nadav Rotem2013-03-021-0/+75
| | | | | | | | | | | | The LoopVectorizer often runs multiple times on the same function due to inlining. When this happens the loop vectorizer often vectorizes the same loops multiple times, increasing code size and adding unneeded branches. With this patch, the vectorizer during vectorization puts metadata on scalar loops and marks them as 'already vectorized' so that it knows to ignore them when it sees them a second time. PR14448. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176399 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Rewrite a test to count emitted instructions without using -stats"Michael Gottesman2013-03-021-12/+14
| | | | | | | | | This reverts commit aac7922b8fe7ae733d3fe6697e6789fd730315dc. I am reverting the commit since it broke the phase 1 public buildbot for a few hours. http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-nobootstrap-RA/builds/2137 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176394 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix inefficient code generation.Akira Hatanaka2013-03-012-3/+140
| | | | | | | | | | | | | | | This patch eliminates the need to emit a constant move instruction when this pattern is matched: (select (setgt a, Constant), T, F) The pattern above effectively turns into this: (conditional-move (setlt a, Constant + 1), F, T) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176384 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite a test to count emitted instructions without using -statsEli Bendersky2013-03-011-14/+12
| | | | | | | | | Also removed the comments of "should produce..." because they completely don't match the actually produced output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176381 91177308-0d34-0410-b5e6-96231b3b80d8
* Set properties for f128 type.Akira Hatanaka2013-03-011-0/+646
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176378 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite a test to check actual output rather than intermediate implementationEli Bendersky2013-03-011-6/+6
| | | | | | | | | | | | | | | | | | | | detail. The was this test was written, it was relying on an implementation detail (fixups) and hence was very brittle (relying, among other things, on the exact ordering of statistics printed by MC). The test was rewritten to check a more observable output difference. While it doesn't cover 100% of the things the original test covered, it's a good practice to write regression tests this way. If we want to check that internal details and invariants hold, such tests should be expressed as unit tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176377 91177308-0d34-0410-b5e6-96231b3b80d8
* No need to force-create clang-tools-extra lit.site.cfgEdwin Vane2013-03-011-5/+0
| | | | | | | | | | | The make (all) target takes care of creating lit configs and auto-generating tests. The problem with the original 'lit.site.cfg' target is it's not recursive and doesn't fully create everything necessary for testing clang-tools-extra. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176374 91177308-0d34-0410-b5e6-96231b3b80d8
* Add regression tests (WORKSFORME)Michael Liao2013-03-015-0/+76
| | | | | | | | | - These tests wont't crash on trunk but would be better to add them so that they don't break again in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176369 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate an error message instead of asserting or segfaulting when we can'tChad Rosier2013-03-011-0/+14
| | | | | | | handle indirect register inputs. rdar://13322011 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176367 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: Don't hang forever if a PHI only has skipped PHI uses.Benjamin Kramer2013-03-011-0/+29
| | | | | | Fixes PR15384. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176366 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10475Michael Liao2013-03-011-0/+30
| | | | | | | | | | | | | | | | - ISD::SHL/SRL/SRA must have either both scalar or both vector operands but TLI.getShiftAmountTy() so far only return scalar type. As a result, backend logic assuming that breaks. - Rename the original TLI.getShiftAmountTy() to TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to return target-specificed scalar type or the same vector type as the 1st operand. - Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for using non-pic code for arm and thumb1 when emitting the sjljChad Rosier2013-03-011-0/+89
| | | | | | | | | dispatch code. As far as I can tell the thumb2 code is behaving as expected. I was able to compile and run the associated test case for both arm and thumb1. rdar://13066352 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176363 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: fix sampler tests after fixing wait insertionsChristian Konig2013-03-011-15/+15
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176359 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add constant extender support framework.Jyotsna Verma2013-03-012-0/+61
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176358 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Remove unused option. Fix 80-column violations.Akira Hatanaka2013-03-011-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176330 91177308-0d34-0410-b5e6-96231b3b80d8
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