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path: root/utils/TableGen/EDEmitter.cpp
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* Fix the encoding of VLD4-dup alignment.Bob Wilson2010-11-301-0/+1
* Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ...Jason W Kim2010-11-181-0/+1
* Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling2010-11-171-0/+4
* ARM fixup encoding for direct call instructions (BL).Jim Grosbach2010-11-111-0/+2
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-031-2/+2
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-9/+7
* Shifter ops are not always free. Do not fold them (especially to formEvan Cheng2010-10-271-0/+1
* Provide correct encodings for NEON vcvt, which has its own special immediate ...Owen Anderson2010-10-271-0/+1
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-0/+4
* ARM mode encoding information for UBFX and SBFX instructions.Jim Grosbach2010-10-151-0/+1
* Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach2010-10-131-0/+1
* Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.Jim Grosbach2010-10-131-0/+2
* Fix spelling error.Cameron Esfahani2010-10-121-2/+2
* trailing whitespaceJim Grosbach2010-10-051-95/+95
* fix bugs in push/pop segment support, rdar://8407242Chris Lattner2010-09-081-4/+12
* remove dead code.Chris Lattner2010-09-011-37/+0
* Rename sat_shift operand to shift_imm, in preparation for using it for otherBob Wilson2010-08-161-1/+1
* Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen2010-08-121-0/+1
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-111-0/+1
* Many Thumb2 instructions can reference the full ARM register set (i.e.,Jim Grosbach2010-07-301-0/+1
* remove option from tablegen for building static header.Chris Lattner2010-07-201-18/+0
* Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!Bruno Cardoso Lopes2010-07-191-0/+1
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-091-0/+2
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-071-0/+1
* Add support for the x86 instructions "pusha" and "popa".Nico Weber2010-06-231-0/+4
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-0/+1
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-4/+1
* Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng2010-05-141-0/+1
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-061-2/+1
* Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coa...Evan Cheng2010-05-061-2/+3
* Fixes to edis that mark x86 call targets asSean Callanan2010-04-231-2/+2
* EDis: Don't include inttypes.h. We support compilers which don't provide it. ...Benjamin Kramer2010-04-141-2/+0
* Fixed a nasty layering violation in the edis sourceSean Callanan2010-04-131-51/+53
* Use errs instead of fprintf.Benjamin Kramer2010-04-081-5/+4
* Added support for ARM disassembly to edis.Sean Callanan2010-04-081-169/+410
* change Target.getInstructionsByEnumValue to return a referenceChris Lattner2010-03-191-2/+2
* Check in tablegen changes to fix disassembler related failures caused by r98465.Evan Cheng2010-03-141-0/+4
* Updated the enhanced disassembly library's TableGenSean Callanan2010-02-101-8/+1
* Updated the TableGen emitter for the EnhancedSean Callanan2010-02-101-209/+24
* Fixed some indentation in the AsmWriterInstSean Callanan2010-02-091-0/+1
* Quick fix to make the header file for the enhancedSean Callanan2010-01-291-3/+3
* Added a custom TableGen backend to support theSean Callanan2010-01-291-0/+856
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