external_llvm.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	Make x86 asm parser to check for xmm vs ymm for index register in gather inst...	Craig Topper	2012-07-18	1	-2/+5
*	X86: add GATHER intrinsics (AVX2) in LLVM	Manman Ren	2012-06-26	1	-0/+2
*	Write llvm-tblgen backends as functions instead of sub-classes.	Jakob Stoklund Olesen	2012-06-11	1	-161/+174
*	Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocess...	Silviu Baranga	2012-04-18	1	-0/+1
*	Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.	Craig Topper	2012-04-03	1	-0/+1
*	Spill DPair registers, not just QPR.	Jakob Stoklund Olesen	2012-03-28	1	-0/+1
*	ARM more NEON VLD/VST composite physical register refactoring.	Jim Grosbach	2012-03-06	1	-1/+1
*	ARM refactor more NEON VLD/VST instructions to use composite physregs	Jim Grosbach	2012-03-06	1	-1/+1
*	ARM Refactor VLD/VST spaced pair instructions.	Jim Grosbach	2012-03-05	1	-2/+1
*	ARM refactor away a bunch of VLD/VST pseudo instructions.	Jim Grosbach	2012-03-05	1	-0/+1
*	Add X86 assembler and disassembler support for AMD SVM instructions. Original...	Craig Topper	2012-02-18	1	-0/+2
*	Make the EDis tables const.	Benjamin Kramer	2012-02-11	1	-5/+1
*	ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).	Jim Grosbach	2011-12-22	1	-0/+2
*	ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.	Jim Grosbach	2011-12-21	1	-0/+1
*	ARM: NEON SHLL instruction immediate operand range checking.	Jim Grosbach	2011-12-07	1	-0/+6
*	ARM NEON VEXT aliases for data type suffices.	Jim Grosbach	2011-12-02	1	-0/+2
*	ARM parsing for VLD1 two register all lanes, no writeback.	Jim Grosbach	2011-11-30	1	-0/+1
*	llvm_unreachable() is not for user diagnostics....	Jim Grosbach	2011-11-30	1	-1/+1
*	ARM parsing aliases for VLD1 single register all lanes.	Jim Grosbach	2011-11-30	1	-0/+1
*	Add vmov.f32 to materialize f32 immediate splats which cannot be handled by	Evan Cheng	2011-11-15	1	-0/+1
*	Assembly parsing for 2-register sequential variant of VLD2.	Jim Grosbach	2011-10-21	1	-0/+1
*	Assembly parsing for 4-register variant of VLD1.	Jim Grosbach	2011-10-21	1	-0/+1
*	Assembly parsing for 3-register variant of VLD1.	Jim Grosbach	2011-10-21	1	-0/+1
*	ARM VLD parsing and encoding.	Jim Grosbach	2011-10-21	1	-0/+1
*	ARM VTBL (one register) assembly parsing and encoding.	Jim Grosbach	2011-10-18	1	-0/+1
*	ARM assembly parsing and encoding for VMOV.i64.	Jim Grosbach	2011-10-18	1	-0/+1
*	ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.	Jim Grosbach	2011-10-18	1	-0/+2
*	ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.	Jim Grosbach	2011-10-17	1	-0/+1
*	ARM NEON "vmov.i8" immediate assembly parsing and encoding.	Jim Grosbach	2011-10-17	1	-0/+1
*	ARM parsing and encoding for the <option> form of LDC/STC instructions.	Jim Grosbach	2011-10-12	1	-0/+1
*	Emit full ED initializers even for pseudo-instructions.	Jakob Stoklund Olesen	2011-10-10	1	-14/+14
*	Insert dummy ED table entries for pseudo-instructions.	Jakob Stoklund Olesen	2011-10-10	1	-3/+3
*	ARM NEON assembly parsing and encoding for VDUP(scalar).	Jim Grosbach	2011-10-07	1	-0/+3
*	Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This w...	Craig Topper	2011-10-06	1	-0/+3
*	Move TableGen's parser and entry point into a library	Peter Collingbourne	2011-10-01	1	-1/+1
*	ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.	Owen Anderson	2011-09-26	1	-0/+1
*	Thumb2 assembly parsing and encoding for TBB/TBH.	Jim Grosbach	2011-09-19	1	-0/+2
*	Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.	Jim Grosbach	2011-09-09	1	-0/+1
*	Thumb2 assembly parsing and encoding for LDRBT.	Jim Grosbach	2011-09-07	1	-0/+1
*	Thumb2 parsing and encoding for LDR(immediate).	Jim Grosbach	2011-09-07	1	-0/+1
*	Improve encoding support for BLX with immediat eoperands, and fix a BLX decod...	Owen Anderson	2011-08-26	1	-0/+1
*	Thumb parsing and encoding support for ADD SP instructions.	Jim Grosbach	2011-08-24	1	-1/+2
*	Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.	Jim Grosbach	2011-08-24	1	-0/+1
*	Create a new register class for the set of all GPRs except the PC. Use it to...	Owen Anderson	2011-08-09	1	-0/+1
*	Fix encodings for Thumb ASR and LSR immediate operands. They encode the rang...	Owen Anderson	2011-08-08	1	-0/+2
*	LDCL_POST and STCL_POST need one's-complement offsets, rather than two's comp...	Owen Anderson	2011-08-04	1	-0/+1
*	ARM refactoring assembly parsing of memory address operands.	Jim Grosbach	2011-08-03	1	-2/+4
*	ARM: rename addrmode7 to addr_offset_none.	Jim Grosbach	2011-08-02	1	-1/+1
*	Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.	Kevin Enderby	2011-07-27	1	-0/+1
*	Split am2offset into register addend and immediate addend forms, necessary fo...	Owen Anderson	2011-07-26	1	-1/+2