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* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-1012/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-161-0/+1
| | | | | | | | | | | This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-1/+2
| | | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko2012-09-121-20/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163721 91177308-0d34-0410-b5e6-96231b3b80d8
* Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper2012-07-181-2/+5
| | | | | | instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: add GATHER intrinsics (AVX2) in LLVMManman Ren2012-06-261-0/+2
| | | | | | | | | | | | | Support the following intrinsics: llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256 llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256 Modified Disassembler to handle VSIB addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-161/+174
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158311 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed decoding for the ARM cdp2 instruction. The restriction on the ↵Silviu Baranga2012-04-181-0/+1
| | | | | | coprocessor number was removed for this instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.Craig Topper2012-04-031-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
* Spill DPair registers, not just QPR.Jakob Stoklund Olesen2012-03-281-0/+1
| | | | | | | | | The arm_neon intrinsics can create virtual registers from the DPair register class which allows both even-odd and odd-even D-register pairs. This fixes PR12389. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153603 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-061-1/+1
| | | | | | Register pair, all lanes subscripting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152157 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-1/+1
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152150 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-051-2/+1
| | | | | | Use the new composite physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152063 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-0/+1
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-181-0/+2
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the EDis tables const.Benjamin Kramer2012-02-111-5/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+2
| | | | | | rdar://10558523 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-211-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: NEON SHLL instruction immediate operand range checking.Jim Grosbach2011-12-071-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON VEXT aliases for data type suffices.Jim Grosbach2011-12-021-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145726 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-301-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm_unreachable() is not for user diagnostics....Jim Grosbach2011-11-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145465 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach2011-11-301-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145464 91177308-0d34-0410-b5e6-96231b3b80d8
* Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng2011-11-151-0/+1
| | | | | | | integer variants. rdar://10437054 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-211-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-0/+1
| | | | | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-181-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142441 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMOV.i64.Jim Grosbach2011-10-181-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.Jim Grosbach2011-10-181-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.Jim Grosbach2011-10-171-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON "vmov.i8" immediate assembly parsing and encoding.Jim Grosbach2011-10-171-0/+1
| | | | | | | | | NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-121-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit full ED initializers even for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-14/+14
| | | | | | This should unbreak the picky buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141575 91177308-0d34-0410-b5e6-96231b3b80d8
* Insert dummy ED table entries for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-3/+3
| | | | | | | | | | The table is indexed by opcode, so simply removing pseudo-instructions creates a wrong mapping from opcode to table entry. Add a test case for xorps which has a very high opcode that exposes this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-071-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This ↵Craig Topper2011-10-061-0/+3
| | | | | | was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-261-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach2011-09-191-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDRBT.Jim Grosbach2011-09-071-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 parsing and encoding for LDR(immediate).Jim Grosbach2011-09-071-0/+1
| | | | | | | | | | The immediate offset of the non-writeback i8 form (encoding T4) allows negative offsets only. The positive offset form of the encoding is the LDRT instruction. Immediate offsets in the range [0,255] use encoding T3 instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-261-0/+1
| | | | | | decoding bug this uncovered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb parsing and encoding support for ADD SP instructions.Jim Grosbach2011-08-241-1/+2
| | | | | | | | Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-0/+1
| | | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
* Create a new register class for the set of all GPRs except the PC. Use it ↵Owen Anderson2011-08-091-0/+1
| | | | | | to tighten our decoding of BFI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encodings for Thumb ASR and LSR immediate operands. They encode the ↵Owen Anderson2011-08-081-0/+2
| | | | | | range 1-32, with 32 encoded as 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
* LDCL_POST and STCL_POST need one's-complement offsets, rather than two's ↵Owen Anderson2011-08-041-0/+1
| | | | | | complement offsets. Add an appropriate immediate type for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
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