| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | - Add "Bitcast" target instruction property for instructions which perform | Evan Cheng | 2011-03-15 | 1 | -0/+1 |
| * | Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, | Evan Cheng | 2010-11-17 | 1 | -0/+1 |
| * | factor the operand list (and related fields/operations) out of | Chris Lattner | 2010-11-01 | 1 | -16/+16 |
| * | Revert r114703 and r114702, removing the isConditionalMove flag from instruct... | Owen Anderson | 2010-09-23 | 1 | -1/+0 |
| * | Add an TargetInstrDesc bit to indicate that a given instruction is a conditio... | Owen Anderson | 2010-09-23 | 1 | -0/+1 |
| * | Add back in r109901, which adds a Compare flag to the target instructions. It's | Bill Wendling | 2010-08-08 | 1 | -0/+1 |
| * | Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn't | Bill Wendling | 2010-08-06 | 1 | -1/+0 |
| * | Add a "Compare" flag to the target instruction descriptor. This will be used | Bill Wendling | 2010-07-30 | 1 | -0/+1 |
| * | Start TargetRegisterClass indices at 0 instead of 1, so that | Dan Gohman | 2010-06-18 | 1 | -1/+2 |
| * | How about ULL... | Eric Christopher | 2010-06-09 | 1 | -1/+1 |
| * | Reapply r105521, this time appending "LLU" to 64 bit | Bruno Cardoso Lopes | 2010-06-08 | 1 | -1/+1 |
| * | Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. | Jakob Stoklund Olesen | 2010-04-05 | 1 | -72/+12 |
| * | Teach TableGen to understand X.Y notation in the TSFlagsFields strings. | Jakob Stoklund Olesen | 2010-03-25 | 1 | -1/+1 |
| * | Finally change the instruction looking map to be a densemap from | Chris Lattner | 2010-03-19 | 1 | -7/+1 |
| * | make inst_begin/inst_end iterate over InstructionsByEnumValue. | Chris Lattner | 2010-03-19 | 1 | -2/+2 |
| * | revert 98912 | Chris Lattner | 2010-03-19 | 1 | -2/+2 |
| * | make inst_begin/inst_end iterate over InstructionsByEnumValue. | Chris Lattner | 2010-03-19 | 1 | -2/+2 |
| * | change Target.getInstructionsByEnumValue to return a reference | Chris Lattner | 2010-03-19 | 1 | -2/+2 |
| * | Introduce a new CodeGenInstruction::ConstraintInfo class | Chris Lattner | 2010-02-10 | 1 | -1/+14 |
| * | move target-independent opcodes out of TargetInstrInfo | Chris Lattner | 2010-02-09 | 1 | -1/+1 |
| * | Remove DEBUG_DECLARE, looks like we don't need it. | Dale Johannesen | 2010-01-15 | 1 | -2/+1 |
| * | Add DEBUG_DECLARE. Not used yet. | Dale Johannesen | 2010-01-09 | 1 | -1/+2 |
| * | Add DEBUG_VALUE. Not used yet. | Dale Johannesen | 2010-01-08 | 1 | -1/+2 |
| * | Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a | Dan Gohman | 2009-10-29 | 1 | -2/+1 |
| * | Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When | Evan Cheng | 2009-10-01 | 1 | -0/+2 |
| * | Introduce the TargetInstrInfo::KILL machine instruction and get rid of the | Jakob Stoklund Olesen | 2009-09-28 | 1 | -1/+1 |
| * | prune the #includes in raw_ostream.h by moving a | Chris Lattner | 2009-08-24 | 1 | -0/+1 |
| * | 1. Introduce a new TargetOperandInfo::getRegClass() helper method | Chris Lattner | 2009-07-29 | 1 | -0/+3 |
| * | make ptr_rc derive from a new PointerLikeRegClass tblgen class. | Chris Lattner | 2009-07-29 | 1 | -1/+1 |
| * | Replace std::iostreams with raw_ostream in TableGen. | Daniel Dunbar | 2009-07-03 | 1 | -8/+7 |
| * | Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize | Dan Gohman | 2009-04-13 | 1 | -1/+1 |
| * | Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS. | Dan Gohman | 2009-04-13 | 1 | -1/+2 |
| * | Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. | Dan Gohman | 2008-12-03 | 1 | -1/+1 |
| * | Add RCBarriers to TargetInstrDesc. It's a list of register classes the given ... | Evan Cheng | 2008-10-17 | 1 | -1/+55 |
| * | Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating | Dan Gohman | 2008-07-01 | 1 | -1/+3 |
| * | Teach the DAGISelEmitter to not compute the variable_ops operand | Dan Gohman | 2008-05-31 | 1 | -12/+0 |
| * | Fix a tblgen problem handling variable_ops in tblgen instruction | Dan Gohman | 2008-05-29 | 1 | -0/+12 |
| * | Add a flag to indicate that an instruction is as cheap (or cheaper) than a move | Bill Wendling | 2008-05-28 | 1 | -13/+14 |
| * | Move instruction flag inference out of InstrInfoEmitter and into | Dan Gohman | 2008-04-03 | 1 | -133/+4 |
| * | Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs... | Christopher Lamb | 2008-03-16 | 1 | -1/+2 |
| * | Remove isImplicitDef TargetInstrDesc flag. | Evan Cheng | 2008-03-15 | 1 | -1/+0 |
| * | Replace all target specific implicit def instructions with a target independe... | Evan Cheng | 2008-03-15 | 1 | -1/+2 |
| * | SDIsel processes llvm.dbg.declare by recording the variable debug information... | Evan Cheng | 2008-02-02 | 1 | -0/+1 |
| * | Simplify the side effect stuff a bit more and make licm/sinking | Chris Lattner | 2008-01-10 | 1 | -2/+1 |
| * | Start inferring side effect information more aggressively, and fix many bugs ... | Chris Lattner | 2008-01-10 | 1 | -22/+33 |
| * | if an instr lacks a pattern, assume it has side effects (unless never has s-e... | Chris Lattner | 2008-01-10 | 1 | -1/+4 |
| * | start inferring 'no side effects'. | Chris Lattner | 2008-01-10 | 1 | -54/+57 |
| * | Infer mayload | Chris Lattner | 2008-01-10 | 1 | -3/+13 |
| * | realize that instructions who match intrinsics that read memory read memory. | Chris Lattner | 2008-01-10 | 1 | -3/+12 |
| * | add a mayLoad property for machine instructions, a correlary to mayStore. | Chris Lattner | 2008-01-08 | 1 | -12/+12 |
