aboutsummaryrefslogtreecommitdiffstats
path: root/utils/TableGen
Commit message (Expand)AuthorAgeFilesLines
* Remove some unnecessary filtering checks from X86 disassembler table build.Craig Topper2011-11-191-35/+8
* Rename MVT::untyped to MVT::Untyped to match similar nomenclature.Owen Anderson2011-11-161-1/+1
* Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng2011-11-151-0/+1
* ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.Jim Grosbach2011-11-152-5/+19
* Tidy up. Formatting.Jim Grosbach2011-11-151-1/+1
* LLVMBuild: Alphabetize required_libraries lists.Daniel Dunbar2011-11-111-1/+1
* Remove this from the CMake build since I erased the file.Owen Anderson2011-11-101-1/+0
* Remove the old-style ARM disassembler, which is no longer used.Owen Anderson2011-11-094-1847/+0
* More AVX2 instructions and their intrinsics.Craig Topper2011-11-062-4/+12
* build: Add initial cut at LLVMBuild.txt files.Daniel Dunbar2011-11-031-0/+23
* The TableGen parts of the CMake build are seriously broken. This fixesChandler Carruth2011-11-021-0/+1
* Allow InstAlias's to use immediate matcher patterns that xform the value.Jim Grosbach2011-10-282-5/+29
* Allow register classes to match a containing class in InstAliases.Jim Grosbach2011-10-281-0/+9
* Delete dead code. Nothing ever instantiates this.Jim Grosbach2011-10-271-4/+0
* Add X86 RORX instructionCraig Topper2011-10-231-14/+23
* Move various generated tables into read-only memory, fixing up const correctn...Benjamin Kramer2011-10-223-23/+28
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-211-0/+1
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-0/+1
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-0/+1
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-0/+1
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-181-0/+1
* ARM assembly parsing and encoding for VMOV.i64.Jim Grosbach2011-10-181-0/+1
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.Jim Grosbach2011-10-181-0/+2
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.Jim Grosbach2011-10-171-0/+1
* ARM NEON "vmov.i8" immediate assembly parsing and encoding.Jim Grosbach2011-10-171-0/+1
* Fix unused variable warning in the rare circumstance that we have no feature-...Owen Anderson2011-10-171-1/+4
* Pick low-hanging MatchEntry shrinkage fruit.Benjamin Kramer2011-10-171-4/+17
* Add X86 PEXTR and PDEP instructions.Craig Topper2011-10-161-18/+27
* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-162-15/+11
* Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMR...Craig Topper2011-10-161-4/+0
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3...Craig Topper2011-10-162-6/+21
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ...Craig Topper2011-10-151-8/+50
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-141-0/+2
* Ban rematerializable instructions with side effects.Jakob Stoklund Olesen2011-10-141-0/+6
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-121-0/+1
* Remove extra semicolon.Eli Friedman2011-10-111-1/+1
* Fix disassembling of popcntw. Also remove some code that says it accounts for...Craig Topper2011-10-112-2/+15
* Emit full ED initializers even for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-14/+14
* Insert dummy ED table entries for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-3/+3
* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-071-0/+3
* Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 6...Craig Topper2011-10-071-0/+1
* Remove the Clang tblgen backends from LLVM.Peter Collingbourne2011-10-0614-4019/+0
* Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This w...Craig Topper2011-10-062-0/+9
* Build system infrastructure for multiple tblgens.Peter Collingbourne2011-10-062-16/+2
* Remove the TRI::getSubRegisterRegClass() hook.Jakob Stoklund Olesen2011-10-061-27/+2
* Add TRI::getSubClassWithSubReg(RC, Idx) function.Jakob Stoklund Olesen2011-10-053-6/+67
* Properly use const_iterator.Jakob Stoklund Olesen2011-10-041-4/+4
* Teach TableGen to infer missing register classes.Jakob Stoklund Olesen2011-10-042-17/+194
* TableGen: Store all allocation orders together.Jakob Stoklund Olesen2011-10-042-14/+15
* TableGen: Privatize CodeGenRegisterClass::TheDef and Name.Jakob Stoklund Olesen2011-10-045-29/+32
generated by cgit v1.1 at 2025-01-09 11:52:46 +0000